ADAU1445 Analog Devices, ADAU1445 Datasheet - Page 75

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ADAU1445

Manufacturer Part Number
ADAU1445
Description
Manufacturer
Analog Devices
Datasheet

Specifications of ADAU1445

Instructions/cycles
3584
Digital I/o Channels
24/24
Analog I/o Channels
0/0
Product Description
Digital audio processor with flexible audio routing matrix, 8 × 2-channel ASRC

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Other Pad Strength Register (Address 0xE24C)
This register controls the pad drive strength of the communications port, S/PDIF output, and master clock outputs. The default 2 mA
setting should be adequate for most applications. The 6 mA setting should be used only when the inte
Table 75. Bit Descriptions of Other Pad Strength Register
Bit Position
[15:7]
6
5
4
3
2
1
0
Description
Reserved
SCL/CCLK
0 = low strength (2 mA)
1 = high strength (6 mA)
CLATCH
0 = low strength (2 mA)
1 = high strength (6 mA)
ADDR1/CDATA
0 = low strength (2 mA)
1 = high strength (6 mA)
ADDR0
0 = low strength (2 mA)
1 = high strength (6 mA)
SDA/COUT
0 = low strength (2 mA)
1 = high strength (6 mA)
SPDIFO
0 = low strength (2 mA)
1 = high strength (6 mA)
CLKOUT
0 = low strength (2 mA)
1 = high strength (6 mA)
Rev. C | Page 75 of 92
ADAU1442/ADAU1445/ADAU1446
grity of the signal is compromised.
Default
0
0
0
0
0
0
0

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