TEF6890H/V2,557 NXP Semiconductors, TEF6890H/V2,557 Datasheet - Page 26

• Manufacturer Part Number: TEF6890H/V2,557
• Description: IC RADIO SIGNAL PROC 44-QFP
• Manufacturer: NXP Semiconductors
• Type: Car Signal Processorr

Specifications of TEF6890H/V2,557

• Applications: Automotive Audio
• Mounting Type: Surface Mount
• Package / Case: 44-MQFP, 44-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935272793557; TEF6890H/V2; TEF6890H/V2

Philips Semiconductors
11.1.3
Table 9 Format of data byte 3
Table 10 Description of data byte 3
11.2
Table 11 Format for subaddress byte with default setting
Table 12 Description of subaddress byte
Table 13 Selection of data byte
2003 Oct 21
Car radio integrated signal processor
SA4
0
0
0
0
0
0
0
0
0
0
0
0
USN3
BIT 7
7 to 4
3 to 0
BIT 7
4 to 0
AIOF
BIT
BIT
7
6
5
Write mode
D
ATA BYTE
SA3
0
0
0
0
0
1
1
1
1
1
1
1
SYMBOL
WAM[3:0]
SYMBOL
USN[3:0]
SA[4:0]
USN2
GATE
GATE
SGAT
BIT 6
BIT 6
AIOF
3; USN
0
SA2
0
1
1
1
1
0
0
0
0
1
1
1
AND
Ultrasonic noise detector. USN content of the MPXRDS audio signal; see Fig.5.
Wideband AM detector. WAM content of the LEVEL voltage; see Fig.6.
Auto-increment off. 0 = auto-increment enabled; 1 = auto-increment disabled.
Gate. 0 = I
autogate function; 1 = I
Shortgate. 1 = I
transmission following this control and disabled automatically.
Data byte select. The subaddress value is auto-incremented when AIOF = 0 and will
revert from SA = 30 to SA = 0. SA = 31 can only be accessed via direct subaddress
selection, in which case auto-increment will revert from SA = 31 to SA = 0; see
Table 13.
WAM
SA1
1
0
0
1
1
0
0
1
1
0
0
1
USN1
SGAT
BIT 5
BIT 5
0
2
SA0
C-bus outputs (SDAG and SCLG) are controllable by the shortgate or the
0
0
1
0
1
0
1
0
1
0
1
0
2
C-bus outputs (SDAG and SCLG) are enabled for a single
USN0
BIT 4
BIT 4
SA4
HEX
C
D
A
B
E
2
4
5
6
7
8
9
2
C-bus outputs are enabled.
(1)
26
RDSCLK
CONTROL
CSALIGN
MULTIPATH
SNC
HIGHCUT
SOFTMUTE
RADIO
INPUT/ASI
LOUDNESS
VOLUME
TREBLE
MNEMONIC
WAM3
BIT 3
BIT 3
SA3
DESCRIPTION
DESCRIPTION
clock of RDS/RBDS
control of supply and AF update
alignment of stereo channel separation
control of weak signal sensitivity and timing
alignment of SNC start and slope
alignment of HCC start and slope
alignment soft mute start and slope
control of radio functions
input selector and ASI settings
loudness control
volume control
treble control
WAM2
BIT 2
BIT 2
SA2
ADDRESSED DATA BYTE
WAM1
BIT 1
BIT 1
SA1
Product specification
TEF6890H
WAM0
BIT 0
BIT 0
SA0