STM32F215VG STMicroelectronics, STM32F215VG Datasheet - Page 98

• Manufacturer Part Number: STM32F215VG
• Description: High-performance ARM Cortex-M3 MCU with 1 Mbyte Flash, 120 MHz CPU, ART Accelerator, HW crypto
• Manufacturer: STMicroelectronics

Specifications of STM32F215VG

• 10/100 Ethernet Mac With Dedicated Dma: supports IEEE 1588v2 hardware, MII/RMII

Electrical characteristics
5.3.17
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NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R
Unless otherwise specified, the parameters given in
performed under the ambient temperature and V
in
Table 45.
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
Figure 37. Recommended NRST pin protection
2. The reset network protects the device against parasitic resets.
3. The user must ensure that the level on the NRST pin can go below the V
V
V
V
T
V
V
Table
NF(NRST)
IH(NRST)
IL(NRST)
NRST_OUT
Symbol
F(NRST)
hys(NRST)
to the series resistance must be minimum
Table
R
PU
45. Otherwise the reset is not taken into account by the device.
10.
(1)
(1)
(1)
(1)
PU
NRST pin characteristics
(see
NRST Input low level voltage
NRST Input high level voltage
NRST Schmitt trigger voltage
hysteresis
Weak pull-up equivalent resistor
NRST Input filtered pulse
NRST Input not filtered pulse
Generated reset pulse duration
Table
42).
Parameter
Doc ID 17050 Rev 6
(~10% order)
(2)
.
Reset source
V
Conditions
DD
V
DD
Internal
IN
> 2.7 V
supply voltage conditions summarized
=
Table 45
V
SS
STM32F215xx, STM32F217xx
are derived from tests
IL(NRST)
–0.5
Min
300
30
20
2
-
-
max level specified in
Typ
200
40
-
-
-
-
-
V
DD
Max
100
0.8
50
-
-
-
+0.5
Unit
mV
kΩ
ns
ns
µs
V