ST72324BK2 STMicroelectronics, ST72324BK2 Datasheet - Page 97

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ST72324BK2

Manufacturer Part Number
ST72324BK2
Description
5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST72324BK2

Hdflash Endurance
1 kcycle at 55 °C, data retention 40 years at 85 °C
Clock Sources
crystal/ceramic resonator oscillators, int. RC osc. and ext. clock input
4 Power Saving Modes
Slow, Wait, Active-halt, and Halt
ST72324Bxx
10.4.3
General description
Figure 50
registers:
The SPI is connected to external devices through four pins:
Figure 50. Serial peripheral interface block diagram
Functional description
A basic example of interconnections between a single master and a single slave is
illustrated in
The MOSI pins are connected together and the MISO pins are connected together. In this
way data is transferred serially between master and slave (most significant bit first).
MOSI
MISO
SCK
SS
SPI Control Register (SPICR)
SPI Control/Status Register (SPICSR)
SPI Data Register (SPIDR)
MISO: Master In / Slave Out data
MOSI: Master Out / Slave In data
SCK: Serial Clock out by SPI masters and input by SPI slaves
SS: Slave select: This input signal acts as a ‘chip select’ to let the SPI master
communicate with slaves individually and to avoid contention on the data lines.
Slave SS inputs can be driven by standard I/O ports on the master MCU.
shows the serial peripheral interface (SPI) block diagram. The SPI has three
SOD
Figure
bit
SPIDR
51.
8-bit Shift Register
Read Buffer
Serial clock
generator
Master
control
Data/Address bus
Read
Write
7
SPIF WCOL
SPIE SPE
7
SPR2
OVR
control
state
SPI
Interrupt
request
MODF
MSTR
On-chip peripherals
CPOL
0
CPHA
SOD
SS
SPICR
SPICSR
SSM
SPR1
1
0
SPR0
SSI
97/193
0
0

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