ST7LITE49K2 STMicroelectronics, ST7LITE49K2 Datasheet - Page 43

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ST7LITE49K2

Manufacturer Part Number
ST7LITE49K2
Description
8-bit MCU
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST7LITE49K2

8 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance
10K write/erase cycles guaranteed Data retention
256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention
20 years at 55 °C.
Clock Sources
Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
Five Power Saving Modes
Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow

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ST7LITE49K2
7.3
7.3.1
Note:
Table 6.
Reset sequence manager (RSM)
Introduction
The reset sequence manager includes three RESET sources as shown in
A reset can also be triggered following the detection of an illegal opcode or prebyte code.
Refer to
These sources act on the RESET pin and it is always kept low during the delay phase.
The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory
mapping.
The basic RESET sequence consists of 3 phases as shown in
External RESET source pulse
Internal LVD RESET (Low Voltage Detection)
Internal WATCHDOG RESET
Active Phase depending on the RESET source
256 CPU clock cycle delay (see
Section 12.2.1 on page 189
ST7 clock sources
for further details.
Table
Hardware configuration
C
L1
EXTERNAL
SOURCE
OSC1
OSC1
OSC1
7)
CAPACITORS
LOAD
ST7
ST7
ST7
Supply, reset and clock management
OSC2
OSC2
OSC2
C
L2
Figure
14:
Figure
15:
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