ST7LITE49K2 STMicroelectronics, ST7LITE49K2 Datasheet - Page 67

• Manufacturer Part Number: ST7LITE49K2
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49K2

• 8 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10K write/erase cycles guaranteed Data retention
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow

ST7LITE49K2
9.4.2
Figure 28. Active-halt mode flowchart
1. This delay occurs only if the MCU exits Active-Halt mode by means of a RESET.
2. Peripherals clocked with an external clock source can still be active.
3. Only the Lite timer RTC and AT timer interrupts can exit the MCU from Active-Halt mode.
4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
Halt mode
The Halt mode is the lowest power consumption mode of the MCU. It is entered by
executing the HALT instruction when Active-halt mode is disabled.
The MCU can exit Halt mode on reception of either a specific interrupt (see
ST7LITE49K2 interrupt
or an interrupt, the main oscillator is immediately turned on and the 256 CPU cycle delay is
used to stabilize it. After the start up delay, the CPU resumes operation by servicing the
interrupt or by fetching the Reset vector which woke it up (see
When entering Halt mode, the I bit in the CC register is forced to 0 to enable interrupts.
Therefore, if an interrupt is pending, the MCU wakes immediately.
In Halt mode, the main oscillator is turned off causing all internal processing to be stopped,
including the operation of the on-chip peripherals. All peripherals are not clocked except the
ones which get their clock supply from another clock generator (such as an external or
auxiliary oscillator).
The compatibility of Watchdog operation with Halt mode is configured by the “WDGHALT”
option bit of the option byte. The HALT instruction when executed while the Watchdog
system is enabled, can generate a Watchdog Reset (see
more details).
during the interrupt routine and cleared when the CC register is popped.
mapping) or a Reset. When exiting Halt mode by means of a Reset
HALT INSTRUCTION
(Active-halt enabled)
N
INTERRUPT
Y
3)
OR SERVICE INTERRUPT
256 CPU CLOCK CYCLE
FETCH RESET VECTOR
OSCILLATOR
PERIPHERALS
CPU
OSCILLATOR
PERIPHERALS
CPU
OSCILLATOR
PERIPHERALS
CPU
I BIT
I BIT
I BITS
N
DELAY
RESET
Y
2)
2)
OFF
OFF
OFF
ON
ON
ON
X
ON
ON
ON
X
0
Section 14.1: Option bytes
4)
4)
Figure
Power saving modes
30).
Table 18:
for
67/245