ST72321AR9-Auto STMicroelectronics, ST72321AR9-Auto Datasheet - Page 103

• Manufacturer Part Number: ST72321AR9-Auto
• Description: 8-bit MCU for automotive with 60 Kbyte Flash, 10-bit ADC, timers, SPI, SCI and I2C interfaces
• Manufacturer: STMicroelectronics

Specifications of ST72321AR9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt, Wait and Slow

ST72321xx-Auto
13.3.3
Note:
1
2
3
4
Input capture
In this section, the index, i, may be 1 or 2 because there are two input capture functions in
the 16-bit timer.
The two 16-bit input capture registers (IC1R and IC2R) are used to latch the value of the
free running counter after a transition is detected on the ICAPi pin (see
ICiR register is a read-only register.
The active transition is software programmable through the IEDGi bit of Control Registers
(CRi).
Timing resolution is one count of the free running counter: (f
Procedure:
To use the input capture function select the following in the CR2 register:
●
●
And select the following in the CR1 register:
●
●
When an input capture occurs:
●
●
●
Clearing the input capture interrupt request (that is, clearing the ICFi bit) is done in two
steps:
1.
2.
After reading the ICiHR register, transfer of input capture data is inhibited and ICFi will never
be set until the ICiLR register is also read.
The ICiR register contains the free running counter value which corresponds to the most
recent input capture.
The two input capture functions can be used together even if the timer also uses the two
output compare functions.
In One pulse Mode and PWM mode only Input Capture 2 can be used.
Select the timer clock (CC[1:0]) (see
Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2
pin must be configured as floating input or input with pull-up without interrupt if this
configuration is available).
Set the ICIE bit to generate an interrupt after an input capture coming from either the
ICAP1 pin or the ICAP2 pin
Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the
ICAP1pin must be configured as floating input or input with pull-up without interrupt if
this configuration is available).
ICFi bit is set.
The ICiR register contains the value of the free running counter on the active transition
on the ICAPi pin (see
A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC
register. Otherwise, the interrupt remains pending until both conditions become true.
Reading the SR register while the ICFi bit is set
An access (read or write) to the ICiLR register
ICiR
Figure
Doc ID 13829 Rev 1
47).
MS Byte
ICiHR
Table 61: Timer clock
CPU
selection).
/CC[1:0]).
LS Byte
Figure
ICiLR
46).
16-bit timer
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