ST72321AR9-Auto STMicroelectronics, ST72321AR9-Auto Datasheet - Page 130

• Manufacturer Part Number: ST72321AR9-Auto
• Description: 8-bit MCU for automotive with 60 Kbyte Flash, 10-bit ADC, timers, SPI, SCI and I2C interfaces
• Manufacturer: STMicroelectronics

Specifications of ST72321AR9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt, Wait and Slow

Serial peripheral interface (SPI)
14.6
14.6.1
Note:
Caution:
14.7
Note:
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Low power modes
Table 64.
Using the SPI to wake up the MCU from Halt mode
In slave configuration, the SPI is able to wake up the ST7 device from Halt mode through a
SPIF interrupt. The data received is subsequently read from the SPIDR register when the
software is running (interrupt vector fetch). If multiple data transfers have been performed
before software clears the SPIF bit, then the OVR bit is set by hardware.
When waking up from Halt mode, if the SPI remains in Slave mode, it is recommended to
perform an extra communications cycle to bring the SPI from Halt mode state to normal
state. If the SPI exits from Slave mode, it returns to normal state immediately.
The SPI can wake up the ST7 from Halt mode only if the Slave Select signal (external SS
pin or the SSI bit in the SPICSR register) is low when the ST7 enters Halt mode. So if Slave
selection is configured as external (see
the master drives a low level on the SS pin when the slave enters Halt mode.
Interrupts
Table 65.
The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
SPI End of Transfer event
Master Mode Fault event
Overrun error
Mode
Wait
Halt
Interrupt event
No effect on SPI.
SPI interrupt events cause the device to exit from Wait mode.
SPI registers are frozen.
In Halt mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by
an interrupt with “exit from Halt mode” capability. The data received is subsequently
read from the SPIDR register when the software is running (interrupt vector fetching). If
several data are received before the wake-up event, then an overrun error is generated.
This error can be detected after the fetch of the interrupt routine that woke up the
device.
Effect of low power modes on SPI
SPI interrupt control/wake-up capability
Doc ID 13829 Rev 1
Event flag
MODF
SPIF
OVR
Slave select management on page
Effect
control bit
Enable
SPIE
Exit from
Wait
Yes
ST72321xx-Auto
123), make sure
Exit from
Halt
Yes
No