ST92F150CV1 STMicroelectronics, ST92F150CV1 Datasheet - Page 348

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ST92F150CV1

Manufacturer Part Number
ST92F150CV1
Description
8-bit MCU
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST92F150CV1

Internal Memory
Single Voltage FLASH up to 256 Kbytes, RAM up to 8Kbytes, 1K byte E3 (Emulated EEPROM)
Minimum Instruction Time
83 ns (24 MHz int. clock)

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CONTROLLER AREA NETWORK (bxCAN)
CONTROLLER AREA NETWORK (Cont’d)
TRANSMIT ERROR COUNTER REG. (TECR)
Read Only
Reset Value: 00h
TEC[7:0] is the least significant byte of the 9-bit
Transmit Error Counter implementing part of the
fault confinement mechanism of the CAN protocol.
RECEIVE ERROR COUNTER REG. (RECR)
Page: 00h — Read Only
Reset Value: 00h
REC[7:0] is the Receive Error Counter implement-
ing part of the fault confinement mechanism of the
CAN protocol. In case of an error during reception,
this counter is incremented by 1 or by 8 depending
on the error condition as defined by the CAN stand-
ard. After every successful reception the counter is
decremented by 1 or reset to 120 if its value was
higher than 128. When the counter value exceeds
127, the CAN controller enters the error passive
state.
348/429
9
REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0
TEC7
7
7
TEC6
TEC5
TEC4
TEC3
TEC2
TEC1
TEC0
0
0
CAN DIAGNOSIS REGISTER (CDGR)
All bits of this register are set and clear by soft-
ware.
Read / Write
Reset Value: 0000 0000 (00h)
Bit 3 = RX CAN Rx Signal
- Read
Monitors the actual value of the CAN_RX Pin.
Bit 2 = SAMP Last Sample Point
- Read
The value of the last sample point.
Bit 1 = SILM Silent Mode
- Read/Set/Clear
0: Normal operation
1: Silent Mode
Bit 0 = LBKM Loop Back Mode
- Read/Set/Clear
0: Loop Back Mode disabled
1: Loop Back Mode enabled
7
0
0
0
0
RX
SAMP
SILM
LBKM
0

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