STR912FAZ46 STMicroelectronics, STR912FAZ46 Datasheet - Page 15

• Manufacturer Part Number: STR912FAZ46
• Description: ARM966E-S™ 16/32-Bit Flash MCU with Ethernet, USB, CAN, AC motor control, 4 timers, ADC, RTC, DMA
• Manufacturer: STMicroelectronics

Specifications of STR912FAZ46

• Arm966e-s Risc Core: Harvard architecture, 5-stage pipeline, Tightly-Coupled Memories (SRAM and Flash)

STR91xFAxxx
3.5
3.5.1
3.5.2
3.6
SRAM (64 Kbytes or 96 Kbytes)
A 32-bit wide SRAM resides on the CPU’s Data TCM (D-TCM) interface, providing single-
cycle data accesses. As shown in
Advanced High-performance Bus (AHB). Sharing is controlled by simple arbitration logic to
allow the DMA unit on the AHB to also access the SRAM.
Arbitration
Zero-wait state access occurs for either the D-TCM or the AHB when only one of the two is
requesting SRAM. When both request SRAM simultaneously, access is granted on an
interleaved basis so neither requestor is starved, granting one 32-bit word transfer to each
requestor before relinquishing SRAM to the other. When neither the D-TCM or the AHB are
requesting SRAM, the arbiter leaves access granted to the most recent user (if D-TCM was
last to use SRAM then the D-TCM will not have to arbitrate to get access next time).
The CPU may execute code from SRAM through the AHB. There are no wait states as long
as the D-TCM is not contending for SRAM access and the AHB is not sharing bandwidth
with peripheral traffic. The ARM966E-S CPU core has a small pre-fetch queue built into this
instruction path through the AHB to look ahead and fetch instructions during idle bus cycles.
Battery backup
When a battery is connected to the designated battery backup pin (VBATT), SRAM contents
are automatically preserved when the operating voltage on the main digital supplies (VDD
and VDDQ are lost or sag below the LVD threshold. Automatic switchover to SRAM can be
disabled by firmware if it is desired that the battery will power only the RTC and not the
SRAM during standby.
DMA data movement
DMA channels on the Advanced High-performance Bus (AHB) take full advantage of the
separate data path provided by the Harvard architecture, moving data rapidly and largely
independent of the instruction path. There are two DMA units, one is dedicated to move data
between the Ethernet interface and SRAM, the other DMA unit has eight programmable
channels with 14 request signals to service other peripherals and interfaces (USB, SSP,
ADC, UART, Timers, EMI, and external request pins). Both single word and burst DMA
transfers are supported. Memory-to-memory transfers are supported in addition to memory-
peripheral transfers. DMA access to SRAM is shared with D-TCM accesses, and arbitration
is described in
list descriptor tables. Of the 16 DMA request signals, two are assigned to external inputs.
The DMA unit can move data between external devices and resources inside the STR91xFA
through the EMI bus.
Section
3.5.1. Efficient DMA transfers are managed by firmware using linked
Doc ID 13495 Rev 6
Figure
1, the D-TCM shares SRAM access with the
Functional overview
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