STR912FAZ46 STMicroelectronics, STR912FAZ46 Datasheet - Page 19

• Manufacturer Part Number: STR912FAZ46
• Description: ARM966E-S™ 16/32-Bit Flash MCU with Ethernet, USB, CAN, AC motor control, 4 timers, ADC, RTC, DMA
• Manufacturer: STMicroelectronics

Specifications of STR912FAZ46

• Arm966e-s Risc Core: Harvard architecture, 5-stage pipeline, Tightly-Coupled Memories (SRAM and Flash)

STR91xFAxxx
Table 6.
0 (high priority)
IRQ channel
hardware
priority
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
Each of 4 remaining interrupt requests generated by the wake-up unit (IRQ26 in
derived from groupings of 8 interrupt sources. One group is from GPIO pins P3.2 to P3.7
plus the RTC interrupt and the USB Resume interrupt; the next group is from pins P5.0 to
P5.7; the next group is from pins P6.0 to P6.7; and last the group is from pins P7.0 to P7.7.
This allows individual pins to be assigned directly to vectored IRQ interrupts or one pin
assigned directly to the non-vectored FIQ interrupt.
VIC IRQ channels
VIC input
channel
VIC0.10
VIC0.11
VIC0.12
VIC0.13
VIC0.14
VIC0.15
VIC0.0
VIC0.1
VIC0.2
VIC0.3
VIC0.4
VIC0.5
VIC0.6
VIC0.7
VIC0.8
VIC0.9
VIC1.0
VIC1.1
VIC1.2
VIC1.3
VIC1.4
VIC1.5
VIC1.6
VIC1.7
VIC1.8
CPU Firmware
Ethernet MAC
BROWNOUT
Logic block
TIM Timer 0
TIM Timer 1
TIM Timer 2
TIM Timer 3
CPU Core
CPU Core
Watchdog
UART0
UART1
UART2
SSP0
SSP1
CCU
DMA
USB
USB
CAN
ADC
I2C0
I2C1
RTC
IMC
Doc ID 13495 Rev 6
Logic OR of transmit, receive, and error interrupts of I2C channel
Logic OR of transmit, receive, and error interrupts of I2C channel
Logic OR of Ethernet MAC interrupts via its own dedicated DMA
Logic OR of ICI0_0, ICI0_1, OCI0_0, OCI0_1, Timer overflow
Logic OR of ICI1_0, ICI1_1, OCI1_0, OCI1_1, Timer overflow
Logic OR of ICI2_0, ICI2_1, OCI2_0, OCI2_1, Timer overflow
Logic OR of ICI3_0, ICI3_1, OCI3_0, OCI3_1, Timer overflow
Timeout in WDT mode, Terminal Count in Counter Mode
Logic OR of interrupts from each of the 8 individual DMA
Logic OR of Alarm, Tamper, or Periodic Timer interrupts
Logic OR of 8 Induction Motor Control Unit interrupts
Logic OR of all interrupts from Clock Control Unit
Logic OR of all CAN interface interrupt sources
Logic OR of 5 interrupts from UART channel 0
Logic OR of 5 interrupts from UART channel 1
Logic OR of 5 interrupts from UART channel 2
Logic OR of all interrupts from SSP channel 0
Logic OR of all interrupts from SSP channel 1
Logic OR of high priority USB interrupts
Logic OR of low priority USB interrupts
End of AtoD conversion interrupt
Firmware generated interrupt
Debug Transmit Command
Debug Receive Command
LVD warning interrupt
Interrupt source
channels
channel.
0
1
Functional overview
Table
6) are
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