HM-6617 Intersil Corporation, HM-6617 Datasheet

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HM-6617

Manufacturer Part Number
HM-6617
Description
2k X 8 Cmos Prom
Manufacturer
Intersil Corporation
Datasheet
March 1997
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
Features
• This Circuit is Processed in Accordance to MIL-STD-
• Low Power Standby and Operating Power
• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . . 90/120ns
• Industry Standard Pinout
• Single 5.0V Supply
• CMOS/TTL Compatible Inputs
• High Output Drive . . . . . . . . . . . . . . . . 12 LSTTL Loads
• Synchronous Operation
• On-Chip Address Latches
• Separate Output Enable
• Operating Temperature Range . . . . . . -55
Ordering Information
Pinouts
SBDIP
SLIM SBDIP
CLCC
GND
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 A
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA at 1MHz
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
HM-6617/883 (SBDIP)
10
11
12
1
2
3
4
5
6
7
8
9
PACKAGE
TOP VIEW
24
23
22
21
20
19
18
17
16
15
14
13
V
A8
A9
P
G
A10
E
Q7
Q6
Q5
Q4
Q3
CC
|
Copyright
TEMPERATURE RANGE
-55
-55
-55
o
o
o
NC
Q0
A6
A5
A4
A3
A2
A1
A0
©
C to +125
C to +125
C to +125
Intersil Corporation 1999
10
11
12
13
5
6
7
8
9
14 15
4
o
C to +125
HM-6617/883 (CLCC)
o
o
o
C
C
C
3
16 17 18 19 20
TOP VIEW
2
1
o
C
6-250
32 31 30
HM1-6617B/883
HM6-6617B/883
HM4-6617B/883
HM-6617/883
Description
The HM-6617/883 is a 16,384-bit fuse link CMOS PROM in
a 2K word by 8-bit/word format with “Three-State” outputs.
This PROM is available in the standard 0.600 inch wide 24
pin SBDIP, the 0.300 inch wide slim SBDIP, and the JEDEC
standard 32 pad CLCC.
The HM-6617/883 utilizes a synchronous design technique.
This includes on-chip address latches and a separate output
enable control which makes this device ideal for applications
utilizing recent generation microprocessors. This design
technique, combined with the Intersil advanced self-aligned
silicon gate CMOS process technology offers ultra-low
standby current. Low ICCSB is ideal for battery applications
or other systems with low power requirements.
The Intersil NiCr fuse link technology is utilized on this and
other Intersil CMOS PROMs. This gives the user a PROM
with permanent, stable storage characteristics over the full
industrial and military temperature voltage ranges. NiCr fuse
technology combined with the low power characteristics of
CMOS provides an excellent alternative to standard bipolar
PROMs or NMOS EPROMs.
All bits are manufactured storing a logical “0” and can be
selectively programmed for a logical “1” at any bit location.
90ns
29
28
27
26
25
24
23
22
21
A8
A9
NC
P
G
A10
E
Q7
Q6
HM1-6617B/883
HM6-6617B/883
HM4-6617B/883
NOTE: P should be hardwired to V
NC
A0-A10
E
Q
V
G
P (Note)
CC
PIN
120ns
except during programming.
2K x 8 CMOS PROM
PIN DESCRIPTION
No Connect
Address Inputs
Chip Enable
Data Output
Power (+5V)
Output Enable
Program Enable
DESCRIPTION
File Number
D24.6
D24.3
J32.A
PACKAGE NO.
CC
3016.1

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HM-6617 Summary of contents

Page 1

... Copyright HM-6617/883 Description The HM-6617/883 is a 16,384-bit fuse link CMOS PROM word by 8-bit/word format with “Three-State” outputs. This PROM is available in the standard 0.600 inch wide 24 pin SBDIP, the 0.300 inch wide slim SBDIP, and the JEDEC standard 32 pad CLCC ...

Page 2

... A4 LSB ALL LINES POSITIVE LOGIC: ACTIVE HIGH THREE-STATE BUFFERS: A HIGH OUTPUT ACTIVE ADDRESS LATCHES AND GATED DECODERS: LATCH ON FALLING EDGE OF E GATE ON FALLING EDGE OF G HM-6617/883 GATED 128 x 128 ROW MATRIX 128 DECODER GATED COLUMN G DECODER AND DATA ...

Page 3

... CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. TABLE 1. HM-6617/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested ...

Page 4

... CL 50pF. 3. Typical derating = 5mA/MHz increase in ICCOP. 4. All tests performed with P hardwired to VCC. 5. TAVQV = TELQV + TAVEL. 6. Tested as follows 1MHz, VIH = 2.4V, VIL = 0.8V, IOH = -1mA, IOL = +1mA, VOH TABLE 3. HM-6617/883 AC AND DC ELECTRICAL PERFORMANCE SPECIFICATIONS (NOTES 1, 2) PARAMETER SYMBOL CONDITIONS Input Capacitance ...

Page 5

... TEHEL G xxxxxxxxxxxxxxxxxxxxxxxxxxxx DATA xxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxx OUTPUT xxxxxxxxxxxxxxxxxxxxxxxxxxxx Q0-Q7 Test Circuit DUT C L (NOTE) NOTE: TEST HEAD CAPACITANCE HM-6617/883 TABLE 4. APPLICABLE SUBGROUPS METHOD 100%/5004 100%/5004 100%/5004 100%/5004 Samples/5005 8A, 8B, 9, 10, 11 Samples/5005 TAVQV xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx 1.5V xxxxxxxxxxxxxxxxxxxxxxxxx TELEL ...

Page 6

... GND GND VCC/2 NOTES 100KHz 10%. All resistors = 47k Unless Otherwise Noted. VCC = 5.5V 0.05V 0.01 F min. HM-6617/883 HM-6617/883 (.600 INCH) SBDIP VCC f10 f6 VCC f5 f12 f4 f11 2.4K f1 2.4K 2.4K VCC/2 VCC/2 2.4K 2.4K GND HM-6617/883 CLCC f10 ...

Page 7

... No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com HM-6617/883 GLASSIVATION: Type: SiO 2 Å Thickness: 7k WORST CASE CURRENT DENSITY 1 A/cm HM-6617/883 VCC GND 6-256 Å ...

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