EVX10AS150ATP ETC-unknow, EVX10AS150ATP Datasheet - Page 17

• Manufacturer Part Number: EVX10AS150ATP
• Description: Adc Single 2.5gsps 10-bit Lvds 317-pin Ebga
• Manufacturer: ETC-unknow

2.6.7
e2v semiconductors SAS 2009
Timing Diagram in Simultaneous and Staggered Mode
The order of magnitude of time difference TD1-TD2 is identical to TOD-TDR:
Except that TOD-TDR is frequency independent, whereas TD1 and TD2 are sampling frequency depen-
dent:
For example at 1:4 DMUX ratio, the data pulse width at maximum operating frequency of 2.5 GHz is
4 × 400 ps = 1.6 ns. Assuming TOD = TDR, the rising edge of differential data clock is ideally located at
center of data pulse, with TD1 = TD2 = 800 ps. With a maximum difference of TOD-TDR of ±100 ps over
temperature, and a total of ± 50 ps output Data skew (ADC + Board), this is yielding to a minimum avail-
able time width for TD1 or TD2 pulses of: 800 ps – 150 ps = 650 ps (with 50/50 duty cycle).
EV10AS150A
0954B–BDC–12/09
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