HT45R37V Holtek Semiconductor Inc., HT45R37V Datasheet - Page 27

• Manufacturer Part Number: HT45R37V
• Description: C/r-f Type 8-bit Otp Mcu
• Manufacturer: Holtek Semiconductor Inc.

a prescaler, the value of which is determined by the
Prescaler Rate Select bits TnPSC2~TnPSC0, which are
bits 2~0 in the Timer Control Register. After the other
bits in the Timer Control Register have been setup, the
enable bit TnON or TnON, which is bit 4 of the Timer
Control Register, can be set high to enable the
Timer/Event Counter to run. Each time an internal clock
cycle occurs, the Timer/Event Counter increments by
one. When it is full and overflows, an interrupt signal is
generated and the Timer/Event Counter will reload the
value already loaded into the preload register and con-
tinue counting. The interrupt can be disabled by ensur-
ing that the Timer/Event Counter Interrupt Enable bit in
the corresponding Interrupt Control Register, is reset to
zero.
Configuring the Event Counter Mode
In this mode, a number of externally changing logic
events, occurring on the external timer pin, can be re-
corded by the Timer/Event Counter. To operate in this
mode, the Operating Mode Select bit pair, TnM1/TnM0,
in the Timer Control Register must be set to the correct
value as shown.
In this mode, the external timer pin, is used as the
Timer/Event Counter clock source, however it is not di-
vided by the internal prescaler. After the other bits in the
Timer Control Register have been setup, the enable bit
TnON, which is bit 4 of the Timer Control Register, can
be set high to enable the Timer/Event Counter to run. If
the Active Edge Select bit, TnE, which is bit 3 of the
Timer Control Register, is low, the Timer/Event Counter
will increment each time the external timer pin receives
a low to high transition. If the Active Edge Select bit is
high, the counter will increment each time the external
timer pin receives a high to low transition. When it is full
and overflows, an interrupt signal is generated and the
Timer/Event Counter will reload the value already
loaded into the preload register and continue counting.
The interrupt can be disabled by ensuring that the
Timer/Event Counter Interrupt Enable bit in the
Rev. 1.00
Control Register Operating Mode
Select Bits for the Event Counter Mode
Event Counter Mode Timing Chart
Bit7 Bit6
Timer Mode Timing Chart
0
1
27
corresponding Interrupt Control Register, is reset to
zero.
As the external timer pin is shared with an I/O pin, to en-
sure that the pin is configured to operate as an event
counter input pin, two things have to happen. The first is
to ensure that the Operating Mode Select bits in the
Timer Control Register place the Timer/Event Counter in
the Event Counting Mode, the second is to ensure that
the port control register configures the pin as an input. It
should be noted that in the event counting mode, even if
the microcontroller is in the Power Down Mode, the
Timer/Event Counter will continue to record externally
changing logic events on the timer input pin. As a result
when the timer overflows it will generate a timer interrupt
and corresponding wake-up source.
Configuring the Pulse Width Measurement Mode
In this mode, the Timer/Event Counter can be utilised to
measure the width of external pulses applied to the ex-
ternal timer pin. To operate in this mode, the Operating
Mode Select bit pair, TnM1/TnM0, in the Timer Control
Register must be set to the correct value as shown.
In this mode the internal clock, f
nal clock for the Timer/Event Counter. However, the
clock source, f
a prescaler, the value of which is determined by the
Prescaler Rate Select bits TnPSC2~TnPSC0, which are
bits 2~0 in the Timer Control Register. After the other
bits in the Timer Control Register have been setup, the
enable bit TnON, which is bit 4 of the Timer Control Reg-
ister, can be set high to enable the Timer/Event Counter,
however it will not actually start counting until an active
edge is received on the external timer pin.
If the Active Edge Select bit TnE, which is bit 3 of the
Timer Control Register, is low, once a high to low transi-
tion has been received on the external timer pin, the
Timer/Event Counter will start counting until the external
timer pin returns to its original high level. At this point the
enable bit will be automatically reset to zero and the
Control Register Operating Mode
Select Bits for the Pulse Width
Measurement Mode
SYS
, for the 8-bit timer is further divided by
SYS
, is used as the inter-
October 20, 2009
HT45R37V
Bit7 Bit6
1
1