MX25L3235D Macronix International Co., MX25L3235D Datasheet - Page 10

• Manufacturer Part Number: MX25L3235D
• Description: 32m-bit [x 1/x 2/x 4] Cmos Serial Flash
• Manufacturer: Macronix International Co.

P/N: PM1383
DATA PROTECTION
The MX25L3235D is designed to offer protection against accidental erasure or programming caused by spurious system
level signals that may exist during power transition. During power up the device automatically resets the state machine
in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after
successful completion of specific command sequences. The device also incorporates several features to prevent
inadvertent write cycles resulting from VCC power-up and power-down transition or system noise.
•
• Valid command length checking: The command length will be checked whether it is at byte base and completed on byte
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other
•
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Power-on reset and tPUW: to avoid sudden power switch by system power supply transition, the power-on reset and
tPUW (internal timer) may protect the Flash.
boundary.
command to change data. The WEL bit will return to reset stage under following situation:
- Power-up
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP) command completion
- Continuously Program mode (CP) instruction completion
- Sector Erase (SE) command completion
- Block Erase (BE) command completion
- Chip Erase (CE) command completion
Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing
all commands except Release from deep power down mode command (RDP) and Read Electronic Signature command
(RES).
Advanced Security Features: there are some protection and securuity features which protect content from inadvertent
write and hostile access.
- The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected as read
only. The proected area definition is shown as table of "Protected Area Sizes", the protected areas are more flexible
which may protect various area by setting value of BP0-BP3 bits.
Please refer to table of "protected area sizes".
- The Hardware Proteced Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and SRWD bit. If the
system goes into four I/O read mode, the feature of HPM will be disabled.
I. Block lock protection
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MX25L3235D
REV. 1.1, OCT. 14, 2008