MX25L3235D Macronix International Co., MX25L3235D Datasheet - Page 26

no-image

MX25L3235D

Manufacturer Part Number
MX25L3235D
Description
32m-bit [x 1/x 2/x 4] Cmos Serial Flash
Manufacturer
Macronix International Co.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MX25L3235DM21-10G
Manufacturer:
MXIC
Quantity:
300
Part Number:
MX25L3235DM21-10G
Manufacturer:
MX
Quantity:
1 000
Part Number:
MX25L3235DM2I-10G
Manufacturer:
MXIC
Quantity:
40 000
Part Number:
MX25L3235DM2I-10G
Manufacturer:
MX
Quantity:
20 000
Company:
Part Number:
MX25L3235DM2I-10G
Quantity:
1 700
Part Number:
MX25L3235DM2I-12G
Manufacturer:
MXIC/旺宏
Quantity:
20 000
Part Number:
MX25L3235DMI-128
Manufacturer:
PANASONIC
Quantity:
3 000
Part Number:
MX25L3235DMI-128
Manufacturer:
MX
Quantity:
1 000
Part Number:
MX25L3235DMI-12G
Manufacturer:
MX
Quantity:
582
Part Number:
MX25L3235DMI-12G
Manufacturer:
MXIC
Quantity:
1 000
Part Number:
MX25L3235DMI-12G
Manufacturer:
MX
Quantity:
1 000
Part Number:
MX25L3235DMI-12G
Manufacturer:
MXIC/旺宏
Quantity:
20 000
Part Number:
MX25L3235DZNI-10G
Manufacturer:
MXIC/旺宏
Quantity:
20 000
P/N: PM1383
POWER-ON STATE
The device is at below states when power-up:
The device must not be selected during power-up and power-down stage unless the VCC achieves below correct level:
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change during
power up state. When VCC is lower than VWI (POR threshold voltage value), the internal logic is reset and the flash device
has no response to any command.
For further protection on the device, after VCC reaching the VWI level, a tPUW time delay is required before the device
is fully accessible for commands like write enable(WREN), page program (PP), Continuously Program (CP), sector
erase(SE), chip erase(CE), WRSCUR and write status register(WRSR). If the VCC does not reach the VCC minimum level,
the correct operation is not guaranteed. The write, erase, and program command should be sent after the below time delay:
The device can accept read command after VCC reached VCC minimum and a time delay of tVSL, even time of tPUW
has not passed.
Please refer to the figure of "power-up timing".
Note:
- Standby mode ( please note it is not deep power-down mode)
- Write Enable Latch (WEL) bit is reset
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
- tPUW after VCC reached VWI level
- tVSL after VCC reached VCC minimum level
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is
recommended.(generally around 0.1uF)
- At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response to any
command. The data corruption might occur during the stage while a write, program, erase cycle is in progress.
26
MX25L3235D
REV. 1.1, OCT. 14, 2008

Related parts for MX25L3235D