T7256 Agere Systems, T7256 Datasheet - Page 12

• Manufacturer Part Number: T7256
• Description: (T7234 - T7256) Compliance
• Manufacturer: Agere Systems

T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Functional Overview
The T7234 device provides two interfaces for informa-
tion transfer: the U-interface, the S/T-interface.
The ANSI maintenance controller can operate in fully
automatic or in fully manual mode. In automatic mode,
the device decodes and responds to maintenance
states according to the ANSI requirements. In manual
mode, the device is controlled by an external mainte-
nance decoder that drives the RESET and ILOSS pins
to implement the required maintenance states.
When the T7234 is powered on and there is no activity
on the S/T- or U-interfaces (i.e., no pending activation
request), it automatically enters a low-power IDLE
mode in which it consumes an average of 35 mW.
This mode is exited automatically when an activation or
U maintenance request occurs from the S/T- or U-inter-
faces. The T7234 provides a board-level test capability
that allows functional verification. Finally, an LED driver
output indicates the status of the device during opera-
tion.
8
ISW[18]
U1
U2
Figure 3. U-Interface Frame and Superframe
U3
U-FRAME SPAN = 1.5 ms
(2B+D) x 12 [216 bits]
U-INTERFACE M BITS [48]
U4
U-Interface Frame Structure
Data is transmitted over the U-interface in 240-bit
groups called U frames. Each U frame consists of an
18-bit synchronization word or inverted synchronization
word (SW or ISW), 12 blocks of 2B+D data (216 bits),
and six overhead bits (M bits). A U-interface super-
frame consists of eight U frames grouped together. The
beginning of a U superframe is indicated by the
inverted sync word (ISW). The six overhead bits (M1—
M6) from each of the eight U frames, when taken
together, form the 48 M bits. Figure 3 shows how U
frames, superframes, and M bits are arranged.
Of the 48 M bits, 24 bits form the embedded operations
channel (eoc) for sending messages from the LT to the
NT and responses from the NT to the LT. There are two
eoc messages per superframe with 12 bits per eoc
message (eoc1 and eoc2). Another 12 bits serve as U-
interface control and status bits (UCS). The last 12 bits
form the cyclic redundancy check (CRC) which is cal-
culated over the 2B+D data and the M4 bits of the pre-
vious superframe. Figure 4 and Table 2 show the
different groups of bits in the superframe.
U5
U-SUPERFRAME SPAN = 12 ms
U6
M[6]
U7
Lucent Technologies Inc.
February 1998
U8
5-2476 (C)