T7256 Agere Systems, T7256 Datasheet - Page 22

• Manufacturer Part Number: T7256
• Description: (T7234 - T7256) Compliance
• Manufacturer: Agere Systems

T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Application Briefs
T7234 Reference Circuit
A reference circuit illustrating the T7234 in a stand-
alone NT1 application is shown in Figures 11 and 12.
This depicts a complete stand-alone NT1 design with
the exception of power supply circuitry and power sta-
tus monitoring circuitry. A bill of materials for the sche-
matic is shown in Table 5. Note that specific
applications may vary depending on individual require-
ments.
U-Interface
The U-Interface attaches to the board at RJ-45 connec-
tor J1 (see Figure 11). F1 and VR2 provide overcurrent
and overvoltage protection, respectively. These two
devices in combination with transformer T1 provide
protection levels required by FCC Part 68 and UL*
1459. For an in-depth discussion of protection issues,
the following application notes are helpful.
1. “Overvoltage Protection of Solid-State
2. Protection of Telecommunications Customer
C16 is a 1.0 F dc blocking capacitor that is required
per ANSI T1.601, Section 7.5.2.3. The 250 V rating of
C16 is governed by the maximum breakdown voltage
of VR2, since the capacitor must not break down before
VR2. The resistance of R13 (21 ) and F1 (12 ) pro-
vides a total line-side resistance of 33 , which is
required when using the Lucent 2754H2 transformer
(see the note at the end of Table 5 for information on
R13 values when using other transformers).
On the device side of the U-interface transformer, VR1
provides secondary overvoltage protection of 6.8 V.
Optional capacitors C13 and C14 provide common-
mode noise suppression for applications that are
required to operate in the presence of high common-
mode noise. R6 and R7 provide the necessary external
hybrid resistors.
S/T-Interface
The S/T-interface attaches to the board at RJ-45 con-
nector J2 (see Figure 12). L1 is a high-frequency com-
mon-mode choke used to minimize EMI. R24 and R25
are 100
8.4. Jumper-selectable resistors R26 and R27 provide
18
Subscriber Loop Circuits,” Lucent Analog Line
Card Products Data Book (CA97-006ALC) 800-
372-2447.
Premises Equipment, Raychem
415-361-6900.
terminations required by ITU I.430 Section
†
Corporation,
for a 50
100
where none of the TEs have terminating resistors.
Dual-transformer T2 has a standard footprint that can
accept ISDN transformers from several vendors. On
the device side of the S/T-interface transformer, D2—
D11 and VR3—4 provide overvoltage protection for the
device pins. R20—23 provide current limiting for cases
where one or more of the protection diodes conducts
due to an overvoltage condition. Capacitor C17 pro-
vides suppression of common-mode noise that might
otherwise be introduced onto the receiver input pins,
effectively increasing the receiver's CMRR. Note that
the S/T transformer must have a center tap on the
device side in order to use this scheme. R16 and R17
in combination with R20 and R21, respectively, provide
the 121
transmitter output pin. R18 and R19 are the 10 k ,
10% resistors required on the receiver input pins.
MLT Circuit
The metallic loop termination (MLT) circuit (U3 and
related components in Figure 11) provides a dc termi-
nation for the loop per ANSI T1.601, Section 7.5. R14
and R15 are power resistors used to sink current dur-
ing overvoltage fault conditions. The optoisolater (U2)
provides signal isolation and voltage translation of the
signaling pulses used for NT maintenance modes, per
T1.601, Section 6.5. The T7234 interprets these pulses
via an internal ANSI maintenance state machine, and
responds accordingly. For applications outside North
America, the MLT circuit is not required.
Status LED
D1 in Figure 11 is an LED that is controlled by the
STLED pin of the T7234 and indicates the status of the
device (activating, out-of-sync, etc.). Table 4 and Figure
10 of this data sheet details the possible states of the
STLED pin and the meaning of each state.
Fixed/Adaptive Timing Control
As detailed in Table 1, pin 7 of the T7234 controls
whether the S/T-interface will use fixed or adaptive tim-
ing recovery. When there is no connection to pin 7, an
internal 100 k pull-up holds the pin high, which
causes the chip to default to adaptive timing recovery.
JMP1 is provided (see Figure 11) to change the timing
recovery mode to fixed timing by pulling pin 7 down
through a 5.1 k resistor.
* UL is a registered trademark of Underwriters Laboratories, Inc.
† Raychem is a registered trademark of Raychem Corporation.
termination. This is useful in configurations
of resistance required by the T7234 on each
termination option instead of the standard
Lucent Technologies Inc.
February 1998