ACS8530T Semtech Corporation, ACS8530T Datasheet - Page 20

• Manufacturer Part Number: ACS8530T
• Description: Synchronous Equipment Timing Source for Stratum 2/3E Systems
• Manufacturer: Semtech Corporation

up to 700 seconds acquiring lock (e.g. in a Stratum3E
application) external software will be required to force the
device into Locked mode until phase lock has been
achieved. Without software control, if the device cannot
achieve lock within 100 seconds, the reference is
disqualified and a phase alarm is raised on it. It will then
revert to Holdover mode and another reference source, if
available, will be selected.
DPLL Architecture and Configuration
A Digital PLL gives a stable and consistent level of
performance that can be easily programmed for different
dynamic behavior or operating range. It is not affected by
operating conditions or silicon process variations. Digital
synthesis is used to generate all required SONET/SDH
output frequencies. The digital logic operates at
204.8 MHz that is multiplied up from the external
12.800 MHz oscillator module. Hence the best resolution
of the output signals from the DPLL is one 204.8 MHz
cycle or 4.9 ns.
Additional resolution and lower final output jitter is
provided by a de-jittering Analog PLL that reduces the
4.9 ns p-p jitter from the digital down to 500 ps p-p and
60 ps RMS as typical final outputs measured broadband
(from 10 Hz to 1 GHz).
This arrangement combines the advantages of the
flexibility and repeatability of a DPLL with the low jitter of
an APLL. The DPLLs in the ACS8530 are uniquely very
programmable for all PLL parameters of bandwidth (from
0.5 mHz up to 70 Hz), damping factor (from 1.2 to 20),
frequency acceptance and output range (from 0 to
80 ppm, typically 9.2 ppm), input frequency (12 common
SONET/SDH spot frequencies) and input-to-output phase
offset (in 6 ps steps up to 200 ns). There is no
requirement to understand the loop filter equations or
detailed gain parameters since all high level factors such
as overall bandwidth can be set directly via registers in
the microprocessor interface. No external critical
components are required for either the internal DPLLs or
APLLs, providing another key advantage over traditional
discrete designs.
The T4 DPLL is similar in structure to the T0 DPLL, but
since the T4 is only providing a clock synthesis and input
to output frequency translation function, with no defined
requirement for jitter attenuation or input phase jump
absorption, then its bandwidth is limited to the high end
and the T4 does not incorporate many of the Phase Build-
out and adjustment facilities of the T0 DPLL.
Revision 3.02/November 2005 © Semtech Corp.
ADVANCED COMMUNICATIONS
FINAL
Page 20
TO DPLL Main Features
T4 DPLL Main Features
Two programmable DPLL bandwidth controls (Locked
and Acquisition bandwidth), each with 18 steps from
0.5 mHz to 70 Hz
Programmable damping factor for optional faster
locking and peaking control. Factors = 1.2, 2.5, 5, 10
or 20
Multiple phase lock detectors
Input to output phase offset adjustment
(Master/Slave), ±200 ns, 6 ps resolution step size
PBO phase offset on source switching - disturbance
down to ±5 ns
Detection of phase jump on the current source:
programmable limit from 1 - 3.5 us in 100 ms
Optional automatic Phase Build-out event on a
detected input phase jump
Multi-cycle phase detection and locking,
programmable up to ±8192 UI - improves jitter
tolerance in direct lock mode
Holdover frequency averaging with a choice of
averaging times: 8 minutes or 110 minutes and value
can be read out
Multiple E1 and DS1 outputs supported
Low jitter MFrSync (2 kHz) and FrSync (8 kHz) outputs
2 kHz and 8 kHz on TO1 to TO7 with programmable
pulse width and polarity.
A single programmable DPLL bandwidth control:
18 Hz, 35 Hz, or 70 Hz
Programmable damping factor for optional faster
locking and peaking control. Factors = 1.2, 2.5, 5, 10
or 20
Multiple phase lock detectors
Multi-cycle phase detection and locking,
programmable up to ±8192 UI - improves jitter
tolerance in direct lock mode
DS3/E3 support (44.736 MHz / 34.368 MHz) at same
time as OC-N rates from T0
Low jitter E1/DS1 options at same time as OC-N rates
from T0
Frequencies of n x E1/DS1 including 16 and 12 x E1,
and 16 and 24 x DS1 supported
Low jitter 2 kHz and 8 kHz outputs on TO1 to TO7
Can use the T4 DPLL as an Independent FrSync DPLL
Can use the phase detector in T4 DPLL to measure
the input phase difference between two inputs.
ACS8530 SETS
DATASHEET
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