AD9244-EVAL Analog Devices, AD9244-EVAL Datasheet - Page 14

• Manufacturer Part Number: AD9244-EVAL
• Description: 14-Bit/ 40/65 MSPS Monolithic A/D Converter
• Manufacturer: Analog Devices

REV. PrD 01/22/02
THEORY OF OPERATION
The AD9244 is a high performance, single supply 14-bit
ADC. In addition to high dynamic range Nyquist sam-
pling, it is designed for excellent IF undersampling per-
formance with an input analog bandwidth of 750MHz.
The AD9244 utilizes an eight stage pipeline architecture
with a wideband, calibrated, input sample and hold ampli-
fier (SHA) implemented on a cost-effective CMOS pro-
cess. Each stage of the pipeline, excluding the last, con-
sists of a low resolution flash ADC along with a switched
capacitor DAC and interstage residue amplifier (MDAC).
The MDAC amplifies the difference between the recon-
structed DAC output and the flash input for the next stage
in the pipeline. One bit of redundancy is used in each of
the stages to facilitate digital correction of flash errors.
The last stage simply consists of a flash ADC.
The performance of the AD9244 is greatly enhanced by
the use of active calibration, yielding superb dynamic
performance.
The pipeline architecture allows a greater throughput rate
at the expense of pipeline delay or latency. While the con-
verter captures a new input sample every clock cycle, it
takes eight clock cycles for the conversion to be fully pro-
cessed and appear at the output. This is illustrated in Fig-
ure 1 on page 5. This latency is not a concern in many
applications. The digital output, together with the out-of-
range indicator (OTR), is latched into an output buffer to
drive the output pins. The output drivers of the AD9244
can be configured to interface with +5V or +3V logic
families.
Connecting the DUTY pin to AVDD implements the
internal clock stabilization function in the AD9244. In
this mode, the AD9244 generates its own internal falling
edge to create an internal 50% duty cycle clock, indepen-
dent of the externally applied duty cycle. See the pin func-
tion descriptions on page 6 for details.
If the DUTY pin is connected to ground through a 10K
resistor or left floating (and decoupled), the AD9244 will
use both edges of the external clock in its internal timing
circuitry (see Figure 1 and specification page for exact
timing requirements).
Control of straight binary or two’s complement output
format is accomplished with the DFS pin. See the pin
function descriptions on page 6 for details.
The ADC samples the analog input on the rising edge of
the clock. While clock is low, the input SHA is in sample
mode. When the clock transitions to a high logic level, the
SHA goes into the hold mode. System disturbances just
prior to or immediately after the rising edge of the clock
and/or excessive clock jitter may cause the input SHA to
acquire the wrong value, and should be minimized.
ANALOG INPUT OPERATION
Figure 2 shows the equivalent analog input of the AD9244
which consists of a 750 MHz differential SHA. The dif-
ferential input structure of the SHA is flexible, allowing
the device to be configured for either a differential or
single-ended input. The analog inputs VIN+ and VIN-
are interchangeable, with the exception that reversing the
AD9244
PRELIMINARY TECHNICAL DATA
–14–
Figure 3. Resistors Isolating SHA Input from Op Amp
inputs to the VIN+ and VIN- pins results in a data inver-
sion (complementing the output word).
The optimum noise and dc linearity performance for ei-
ther differential or single-ended inputs is achieved with the
largest input signal voltage span (i.e., 2V input span) and
matched input impedance for VIN+ and VIN-. Only a
slight degradation in dc linearity performance exists be-
tween the 2V and 1V input spans.
High frequency inputs may find the 1V span better suited
to achieve superior SFDR performance. (See Typical
Performance Characteristics.)
When the ADC is driven by an op amp and a capacitive
load is switched onto the output of the op amp, the output
will momentarily drop due to its effective output imped-
ance. As the output recovers, ringing may occur. To rem-
edy the situation, a series resistor can be inserted between
the op amp and the SHA input as shown in Figure 3. A
shunt capacitance also acts like a charge reservoir, sinking
or sourcing the additional charge required by the hold
capacitor, C
the op amp’s output.
The optimum size of this resistor is dependent on several
factors, including the ADC sampling rate, the selected op
amp, and the particular application. In most applications,
a 30
VIN-
VIN+
C PIN,PAR
C PIN,PAR
Figure 2. Analog Input of AD9244 SHA
to 100
V EE
V CC
H
, further reducing current transients seen at
10 F
resistor is sufficient.
S
S
33
R S
0.1 F
33
R S
H
15pF
C S
C S
VIN+
VIN-
VREF
REFSENSE
REFCOM
AD9244
+
-
C H
S
S
C H