AD9396/PCB Analog Devices, AD9396/PCB Datasheet - Page 14

• Manufacturer Part Number: AD9396/PCB
• Description: Analog/dvi Dual-display Interface
• Manufacturer: Analog Devices

AD9396
Power Management
The AD9396 uses the activity detect circuits, the active interface
bits in the serial bus, the active interface override bits, the
power-down bit, and the power-down pin to determine the
correct power state. There are four power states: full-power,
seek mode, auto power-down, and power-down.
Table 8 summarizes how the AD9396 determines the power
mode and the circuitry that is powered on/off in each of these
modes. The power-down command has priority and then the
automatic circuitry. The power-down pin (Pin 81—polarity set
Table 8. Power-Down Mode Descriptions
Mode
Full Power
Seek Mode
Seek Mode
Power-Down
1
2
3
Table 9. Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats
Standard
VGA
SVGA
XGA
SXGA
TV
1
Power-down is controlled via Bit 0 in Serial Bus Register 0x26.
Sync detect is determined by OR’ing Bit 7 to Bit 2 in Serial Bus Register 0x15.
Auto power-down is controlled via Bit 7 in Serial Bus Register 0x27.
These are preliminary recommendations for the analog PLL and are subject to change without notice.
Power-Down
0
1
1
1
Resolution
640 × 480
800 × 600
1024 × 768
1280 × 1024
1280 × 1024
480i
480p
720p
1035i
1080i
1080p
1
Sync Detect
1
0
0
X
Refresh Rate
(Hz)
60
72
75
85
56
60
72
75
85
60
70
75
80
85
60
75
60
60
60
60
60
60
Inputs
2
Auto PD Enable
X
0
1
Horizontal
Frequency (kHz)
31.5
37.7
37.5
43.3
35.1
37.9
48.1
46.9
53.7
48.4
56.5
60.0
64.0
68.3
64.0
80.0
15.75
31.47
45
33.75
33.75
67.5
Rev. 0 | Page 14 of 48
by Register 0x26[3]) can drive the chip into four power-down
options. Bit 2 and Bit 1 of Register 0x26 control these four
options. Bit 0 controls whether the chip is powered down or the
outputs are placed in high impedance mode (with the exception
of SOG). Bit 7 to Bit 4 of Register 0x26 control whether the
outputs, SOG, Sony Philips digital interface (SPDIF ) or I
or Inter-IC sound bus) outputs are in high impedance mode or
not. See the 2-Wire Serial Control Register Detail section for
more detail.
3
Pixel Rate (MHz)
25.175
31.500
31.500
36.000
36.000
40.000
50.000
49.500
56.250
65.000
75.000
78.750
85.500
94.500
108.000
135.000
13.51
27
74.25
74.25
74.25
148.5
Power-On or Comments
Everything
Everything
Serial bus, sync activity detect, SOG, band gap
reference
Serial bus, sync activity detect, SOG, band gap
reference
VCO Range
00
01
01
01
01
01
01
01
01
10
10
10
10
10
10
11
00
00
10
10
10
11
1
Current
101
011
100
100
100
101
110
110
110
011
100
100
101
110
110
110
010
101
100
100
100
110
1
2
S (IIS