AD9396/PCB Analog Devices, AD9396/PCB Datasheet - Page 20

• Manufacturer Part Number: AD9396/PCB
• Description: Analog/dvi Dual-display Interface
• Manufacturer: Analog Devices

AD9396
The functional diagram for a single channel of the CSC, as
shown in Figure 13, is repeated for the remaining G and B
channels. The coefficients for these channels are b1, b2, b3, b4,
c1, c2, c3, and c4.
A programming example and register settings for several
common conversions are listed in the Color Space Converter
(CSC) Common Settings.
For a detailed functional description and more programming
examples, refer to the application note
Space Converter User's Guide.
TIMING DIAGRAMS
The following timing diagrams show the operation of the
AD9396.The output data clock signal is created so that its rising
edge always occurs between data transitions and can be used to
Table 11.
Port
Bit
4:4:4
4:2:2
4:4:4 DDR
4:2:2 to 12
1
Arrows in the table indicate clock edge. Rising edge of clock = ↑, falling edge = ↓.
Red
7
Red/Cr [7:0]
CbCr [7:0]
DDR
DDR
CbCr [11:0]
CB/CROUT
DATAOUT
DATACK
↑
↓
DATACK
6
DATAIN
HSOUT
DATAIN
HSOUT
1
R [7:0]
YOUT
HSIN
HSIN
G [3:0]
5
NOTES:
1. PIXEL AFTER HSOUT CORRESPONDS TO BLUE INPUT.
2. EVEN NUMBER OF PIXEL DELAYS BETWEEN HSOUT AND DATAOUT.
4
P0
P0
3
DDR
AN-795, AD9880 Color
P1
P1
2
↑
B [7:4]
P2
P2
2 CLOCK CYCLE DELAYS
1
2 CLOCK CYCLE DELAYS
0
P3
P3
Figure 15. YCrCb ADC Timing
Green
7
Green/Y [7:0]
Y [7:0]
DDR
DDR
Figure 14. RGB ADC Timing
P4
P4
Rev. 0 | Page 20 of 48
6
↑
↓
B [3:0]
G [7:4]
P5
P5
5
4
P6
P6
latch the output data externally. There is a pipeline in the
AD9396, which must be flushed before valid data becomes
available. This means six data sets are presented before valid
data is available.
R
B
G
IN
IN
IN
[11:0]
[11:0]
[11:0]
3
DDR 4:2:2
DDR 4:2:2
Y [11:0]
P7
P7
2
a2[12:0]
a3[12:0]
a1[12:0]
P8
8 CLOCK CYCLE DELAYS
P8
8 CLOCK CYCLE DELAYS
×
×
×
P0
Y0
B0
1
↑
↓
CbCr [11:0]
Y,Y [11:0]
P9
P9
×
×
×
0
P1
Y1
R0
4096
4096
4096
Figure 13. Single CSC Channel
1
1
1
P10
P10
P2
Y2
B2
+
Blue
7
Blue/Cb [7:0]
DDR 4:2:2
P11
P11
P3
Y3
R2
+
6
a4[12:0]
5
↑
+
CbCr
4
×4
×2
↓
CSC_Mode[1:0]
3
Y, Y
2
1
0
2
R
OUT
1
[11:0]
0