MT92210 Zarlink Semiconductor, MT92210 Datasheet - Page 99

• Manufacturer Part Number: MT92210
• Description: 1023 Channel Voice Over ip (VoIP) Processor
• Manufacturer: Zarlink Semiconductor

Data Sheet
The Underrun Lead and Overrun Lead are used to control the size of slips when they occur. Some algorithms
prefer to place both the Underrun Lead and Overrun Lead at the center of the buffer, which minimizes the number
of slips, but causes large slips and may add as much as (Maximum Used Samples in Circular Buffer / 2) of extra
delay. Another possible algorithm is to place both the Underrun Lead and Init Lead to a small value K (e.g. 8
samples) and the Overrun Lead to (Maximum Used Samples in Circular Buffer - K). This causes slips of 8 bytes,
may results in multiple slips, but ensures that no more than K samples of delay are ever inserted on the data.
The MT92210 PDV monitoring may be used to control the end-to-end delay experienced on a given channel. To do
so, the software initializes the Desired Remote/Local Timestamp Delta field to 0. This gives the expected delta
between the timestamp in the RTP packet and the timestamp on the H.110 bus. The chip then Overruns and
Underruns according to the need and settles within its PDV window. Each slip affects the Total Slip Offset Delta,
which measures by how many samples the actual delta is off from the Desired Remote/Local Timestamp Delta.
Software can then come and fix the Desired Remote/Local Timestamp Delta by adding to it the Total Slip Offset
Delta and resetting the Total Slip Offset Delta. Note that a Total Slip Offset Delta of 12 and a Desired Remote/Local
Timestamp Delta of 35 is the same as a Total Slip Offset Delta of 0 and a Desired Remote/Local Timestamp Delta
of 47.
The Minimum Delta gives the smallest value of Remote vs. Local delta seen so far (Minimum Delta means earliest
packet, so the packet most likely to cause an overrun) while the Maximum Delta gives the largest value of Remote
vs. Local delta seen so far (Maximum Delta means latest packet, so the packet most likely to cause an underrun).
Thanks to this diagnostic, software can choose to change the Desired Remote/Local Timestamp Delta by another
value, if, for example, the Maximum Delta indicates that a packet has been seen that would cause the current delta
values to slip (this might be an indication that the PDV window is too small). If so, this will cause a slip and the
software can choose when it wants the slip to occur. It can occur immediately, by setting the RSO (Reset Total Slip
Offset Delta Once) bit, which will cause it to slip on the next packet. It can also wait for a packet with a marker bit =
'1' by setting the RSM (Reset Total Slip Offset Delta on Marker). Finally, it can choose to reset when a significant
amount of data has been lost by setting the RSL (Reset Total Slip Offset on Loss) bit. The Min Slip field defines
what a “significant” amount of data is in 2
Some application may want the end-to-end delay to be fixed and unchanging, even in the case of slips. If that is the
case, setting the RSA (Reset Total Slip Offset Delta Always) will ensure that the Total Slip Offset Delta never
changes, which disables slips. This could lead to a loss of data integrity in the case of Underruns (or Overruns, but
only if they manage to overflow the entire physical circular buffer, not only the section reserved by Maximum Used
Samples in Circular Buffer).
This end-to-end delay control may be used in several applications:
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The format of the RX RTP Common PDV Absorption structure is the following:
End-to-end slipless framing . This setup allows one or multiple PCM bearers to be transported end-to-end
over a packet network without slips.
Clear-channel DS3 . Because the PDV monitoring allows multiple PCM channels to connect to a single
Common PDV Absorption Structure, up to 1023 individual PCM bearers could use the same PDV
information; this environment could tolerate slips where a single channel could cause a slip on all channels,
maintaining the end-to-end delay across all channels.
Interchip synchronization . Because the desired Remote/Local Timestamp delta is an absolute value (not
relative to anything inside the chip), multiple chips can maintain the same end-to-end delay. The only
requirement here is that all sources be capable of generating synchronized timestamps. MT92210 is
capable of this because multiple chips can slave off the same H.110 bus timestamp.
Glitchless fallback . Because multiple chips can maintain delay consistency, channels and connections can
be swapped from one chip to another without a single byte loss.
n
increments, between 2 ms and 256 ms.
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MT92210
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