SC26L198 Philips Semiconductors, SC26L198 Datasheet
SC26L198
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SC26L198 Summary of contents
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... Product specification SC26C198 SC68C198 SC26L198 SC68L198 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Plastic Leaded Chip Carrier (PLCC) NOTES: 1. For availability, please contact factory. 1995 May 1 SC26C198 SC68C198 SC26L198 SC68L198 IACKN and DACKN signal pins Watch dog timer for each receiver (64 receive clock counts) Programmable Data Formats: – data bits plus parity – ...
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... I/O2a 14 I/O3a 15 TxDa 16 I/O0b 17 I/O1b 18 I/O2b 19 I/O3b 20 TxDb 21 I/O0c 22 Vss 23 I/O1c 24 I/O2c 25 I/O3c 26 TxDc 27 RxDc 28 I/O0d 1995 May 1 SC26C198 SC68C198 SC26L198 SC68L198 84-Pin PLCC TOP VIEW Pin Function 29 I/O1d 30 I/O2d 31 I/O3d 32 RxDd 33 Vss 34 TxDd 35 RESETN 36 Gin0 37 Gout0 38 ...
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... Operation Section of this specification is not implied. 1995 May 1 DESCRIPTION PARAMETER to GND DD = 5.0 Volts CC = 3.3 Volts CC 339 Product specification SC26C198 SC68C198 SC26L198 SC68L198 RATING UNIT See Note 3 C -65 to +150 C -0.5 to +7 ...
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... In all cases the internal action will terminate at the withdrawal of CEN. Synchronous CEN cycles shorter than multiples of four Sclk cycles minus 1 Sclk and asynchronous CEN cycles shorter than four Sclk cycles may cause short read or write cycles and produce corrupted data transfers. 340 Product specification SC26C198 SC68C198 SC26L198 SC68L198 SD00193 ...
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... The formula for calculating ’n’, the number loaded to the BRGTRU and BRGTRL registers, is shown below. 1995 May 1 SC26C198 SC68C198 SC26L198 SC68L198 BRG Timer Input frequency desired baud rate Note: ’n’ may assume values of 0 and 1. In previous Philips data communications controllers these values were not allowed ...
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... These are not real hardware devices. They are defined by the 1995 May 1 SC26C198 SC68C198 SC26L198 SC68L198 content of the CIR (Current Interrupt Register result of an interrupt arbitration. In other words they are indirect registers contained in the Current Interrupt Register (CIR) which the CIR uses to point to the source and context of the OCTART sub circuit presently causing an interrupt ...
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... The MR0[5:4] allow the 1995 May 1 SC26C198 SC68C198 SC26L198 SC68L198 user to modify this characteristic so that bidding will not start until one of four levels (empty, 3/4 empty, 1/2 empty, not full) have been reached. As will be shown later this feature may be used to make slight improvements in the interrupt service efficiency ...
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... The ”Change of State” (COS) detectors are sensitive to both transition. The detectors are controlled by the internal 344 Product specification SC26C198 SC68C198 SC26L198 SC68L198 ...
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... It also drives the Global Registers associated with the interrupt. Most importantly it drives the modification of the Interrupt Vector. The arbitration process is driven by the Sclk. It scans the 10 bits of the arbitration bus at the Sclk rate developing a value for the CIR 345 Product specification SC26C198 SC68C198 SC26L198 SC68L198 ...
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... CIR may be decoded for type, channel 1995 May 1 SC26C198 SC68C198 SC26L198 SC68L198 and character count information. Optionally, the global interrupt registers may be read for particular information about the interrupt status or use of the global RxD and TxD registers for data transfer as appropriate ...
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... It is recommended that this mode be used when initially verifying processor to UART interface. The communication between the transmitter and receiver is entirely within the UART – essentially ”talking to itself”. 347 Product specification SC26C198 SC68C198 SC26L198 SC68L198 B4 B3 Bits 2:0 1 Channel No 1 Channel No ...
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... In the full automatic the internal state machine devoted to this function will handle all operations 1995 May 1 SC26C198 SC68C198 SC26L198 SC68L198 associated with address recognition, data handling, receiver enables and disables. In both modes the meaning of the parity bit is changed often referred to as the A/D bit or the address/data bit used to indicate whether the byte presently in the receiver shift register is an ” ...
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... May 1 SC26C198 SC68C198 SC26L198 SC68L198 In–band flow control is a protocol for controlling a remote transmitter by embedding special characters within the message stream, itself. Two characters, Xon and Xoff, which do not represent normal printable characters take on flow control definitions when the Xon/Xoff capability is enabled ...
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... Xon or Xoff character is not pushed into the RxFIFO. If cleared, the power–on and reset default, the received 1995 May 1 SC26C198 SC68C198 SC26L198 SC68L198 Xon or Xoff character is pushed onto the RxFIFO for examination by the host CPU. The MR0(7) function operates regardless of the value in MR0(3:2) ...
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... Auto Receiver flow control 01 – 3/4 empty 11 – Auto Receiver and Transmitter 10 – 1/2 empty flow control 11 – not full 351 Product specification SC26C198 SC68C198 SC26L198 SC68L198 Bit 0 Power Down Mode 0 – Device enabled 1 – Power down Bit 3:2 Bit 1:0 Address Recognition control 00 – ...
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... This number does not include the start, parity, or stop bits. Bit 4 CTSN Enable Tx RxINT RRDY 1 = Yes 01 = Half Full 10 = 3/4 Full 11 = Full 352 Product specification SC26C198 SC68C198 SC26L198 SC68L198 Bit 2 Bit 1:0 Parity Type Bits per Character 0 = Even 00 – Odd 01 – – – 8 Bit 3:2 Bit 1:0 Stop Length ...
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... Bits 7:5 Reserved 1995 May 1 SC26C198 SC68C198 SC26L198 SC68L198 appropriate commands issued via the command register. MR2[ causes RTSN to be reset automatically one bit time after the characters in the transmit shift register and in the TxFIFO (if any) are completely transmitted (includes the programmed number of stop bits if the transmitter is not enabled) ...
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... I/O2 or I/O1 pin associated with the I/OPIOR register. 01010 Reserved 01011 Reserved 01100 Reserved 354 Product specification SC26C198 SC68C198 SC26L198 SC68L198 Clock selection, CCLK = 3.6864 MHz BRG – 19.2K BRG – 28.2K BRG – 38.4K BRG – 57.6K BRG – 115.2K BRG – 230. ...
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... Xon character registers. This command provides a 1995 May 1 SC26C198 SC68C198 SC26L198 SC68L198 mechanism to initialize all the Xon Character registers to a default value with one write. Execution of this command is immediate and does not effect the timing of subsequent host I/O operations ...
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... RxFIFO is full, RxFULL is not reset until the second read of the RxFIFO since the waiting character is immediately loaded to the RxFIFO. 356 Product specification SC26C198 SC68C198 SC26L198 SC68L198 Channel Command Description Transmit Xon Transmit Xoff Gang Write Xon Character Registers * ...
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... IRQN output being asserted (low). If the corresponding bit in the IMR is a zero, the state of the bit in the ISR has no affect on the IRQN output. 357 Product specification SC26C198 SC68C198 SC26L198 SC68L198 Bit 1 Bit 0 TxRDY Transmitter has entered arbitration process ...
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... Bits of the Multi–Drop Address Character Recognition An 8 bit character register that contains the compare value for the wake–up address character 358 Product specification SC26C198 SC68C198 SC26L198 SC68L198 Bits 2:0 MSB of an Xon/Xoff interrupt bid Bits 2:0 MSB of an address recognition event interrupt bid ...
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... ICR, the Current Interrupt Register, CIR, will contain x’00. Refer to the functional description of 359 Product specification SC26C198 SC68C198 SC26L198 SC68L198 Bits 1:0 TxD character status 00 – normal TxD data 01 – wait on normal data 10 – Xoff in pending 11 – ...
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... CIR. Its numerical value equals the number of bytes minus 1 (count – 1) ready for transfer to the transmitter or transfer from the receiver undefined for other types of interrupts 360 Product specification SC26C198 SC68C198 SC26L198 SC68L198 Bits 7:0 Bits 4:3 Bits 2:0 Will be replaced Replaced with with current ...
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... The following four registers control the function of the G These output pins have a unique control matrix which includes a 361 Product specification SC26C198 SC68C198 SC26L198 SC68L198 Bit 2:0 Other types 000 – not ”other” type 001 – Change of State 010 – Address Recognition Event 011 – ...
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... DATA READ/WRITE RxC16Xa TxC16Xb D INPUT GPOR(0) GPOR(1) QN GPOR(2) GPOR(3) D CLOCK 8:1 MULTIPLEX Figure 1. General Purpose Pin Control Logic 362 Product specification SC26C198 SC68C198 SC26L198 SC68L198 Bits 5:4 Bits 3:2 Bits 1:0 Clk Sel Clk Sel Clk Sel GPOR(2) GPOR(1) GPOR( none 00 = none 00 = none ...
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... Interrupt Vector Register 1995 May 1 SC26C198 SC68C198 SC26L198 SC68L198 UART B that apply to the total chip configuration. The ”Register Map Detail” shows the use of every address in the 8 bit address space. NOTE: The register maps for channels A and B (UARTs A and B) contain some control registers that configure the entire chip ...
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... BCRCOSa Reserved BCRXa BCRAa Address Recognition Character a (ARCRa) Reserved Receiver Clock Select Register a (RxCSRa) Test Register Xmit Clock Select Register a TxCSRa) Global Chip Configuration Reg GCCR) 364 Product specification SC26C198 SC68C198 SC26L198 SC68L198 Acronym Read/Write Page MR2 R ISR ...
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... BCRCOSc Reserved BCRXc BCRAc Reserved Receiver Clock Select Register c (RxCSRc) Reserved Reserved 365 Product specification SC26C198 SC68C198 SC26L198 SC68L198 Write Mode Register 0 MR0b Mode Register 1 MR1b I/O Port Configuration Reg b I/OPCRb BCRBRKb BCRCOSb Reserved BCRXb BCRAb Xon Character Reg b (XonCRb) Xoff Character Reg b (XoffCRb) ...
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... BCRAe Address Recognition Char e (ARCRe) Reserved Receiver Clock Select Register e (RxCSRe) Reserved Xmit Clock Select Register e (TxCSRe) Reserved 366 Product specification SC26C198 SC68C198 SC26L198 SC68L198 Write Mode Register 0 MR0d Mode Register 1 MR1d BCRBRKd BCRCOSd Reserved BCRXd BCRAd Xon Character Reg d (XonCRd) ...
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... Address Recognition Char g (ARCRg) Reserved Receiver Clock Select Register g (RxCSRg) Reserved Xmit Clock Select Register g (TxCSRg) Reserved 367 Product specification SC26C198 SC68C198 SC26L198 SC68L198 Mode Register 0 MR0f Mode Register 1 MR1f I/OPort Configuration Reg f I/OPCRf BCRBRKf BCRCOSf Reserved BCRXf BCRAf Xon Character Reg f (XonCRf) ...
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... Address Recognition Char h (ARCRh) Reserved Receiver Clock Select Register h (RxCSRh) Reserved Xmit Clock Select Register h (TxCSRh) Reserved 368 Product specification SC26C198 SC68C198 SC26L198 SC68L198 Mode Register 0 MR0h Mode Register 1 MR1h BCRBRKh BCRCOSh Reserved BCRXh BCRAh Xon Character Reg h (XonCRh) Xoff Character Reg h (XoffCRh) ...
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... Reserved I/O Port Interrupt and Output b (I/OPIORb) Reserved Reserved Reserved Reserved 369 Product specification SC26C198 SC68C198 SC26L198 SC68L198 Write Mode Register a (MR2a) Command Register a (CRa) Interrupt Mask Register a (IMRa) Transmitter FIFO Reg a (TxFIFOa) BRG Timer Reg Upper a (BRGTRUa) Reserved Reserved GP Out Select Reg (GPOSR) ...
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... I/O Port Interrupt and Output d (I/OPIORd) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 370 Product specification SC26C198 SC68C198 SC26L198 SC68L198 Write Mode Register c (MR2c) Command Register c (CRc) Interrupt Mask Register c (IMRc) Transmitter FIFO Reg c (TxFIFOc) Reserved Reserved Reserved Reserved Reserved Reserved Reserved ...
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... I/O Port Interrupt and Output f (I/OPIORf) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 371 Product specification SC26C198 SC68C198 SC26L198 SC68L198 Write Mode Register e (MR2e) Command Register e (CRe) Interrupt Mask Register e (IMRe) Transmitter FIFO Reg e (TxFIFOe) Reserved Reserved Reserved Reserved Reserved Reserved Reserved ...
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... Transmitters Receivers Interrupts, current and future Halts: BRG Counters Bus cycle in progress (hardware RESET only) 372 Product specification SC26C198 SC68C198 SC26L198 SC68L198 Write Mode Register g (MR2g) Command Register g (CRg) Interrupt Mask Register g (IMRg) Transmitter FIFO Reg g (TxFIFOg) Reserved Reserved Reserved Reserved ...
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... Operating mode I CC Power down mode (no clocks operating) 1995 May 1 SC26C198 SC68C198 SC26L198 SC68L198 The user must allow a minimum of 6 SClk cycles to elapse after a reset (RESETN pin or CRa initiated) of the device terminates before initiating a new bus cycle. LIMITS TEST CONDITIONS TEST CONDITIONS ...
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... Min low time at Vil (0.8V) Tsclkh Min high time at Vih (2.0V) Fsclk Sclk frequency T/RFsclk Sclk rise/fall time (0.8 to 2.0Volts) 1995 May 1 5 (26C198 and 68C198) PARAMETER PARAMETER 374 Product specification SC26C198 SC68C198 SC26L198 SC68L198 LIMITS UNIT UNIT MIN TYP MAX 10 Sclk ...
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... All voltage measurements are relative to gnd. Input and output levels are those shown in “DC Electrical Specifications”. For testing, inputs switch between 0.2 and 2.8V; outputs are measured between 0.8 and 2.0V. 1995 May 1 (Continued) PARAMETER PARAMETER 2 375 Product specification SC26C198 SC68C198 SC26L198 SC68L198 LIMITS UNIT UNIT MIN TYP MAX 0 3.6864 8.0 ...
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... Open-drain output low current in off state ODL I Open drain output high current in off state ODH Power supply current Operating mode I CC Power down mode (no clocks operating) 1995 May 1 SC26C198 SC68C198 SC26L198 SC68L198 LIMITS TEST CONDITIONS TEST CONDITIONS MIN TYP V SS 2.0 0 ...
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... Min high time at Vih (2.0V) Fsclk Sclk frequency T/RFsclk Sclk rise/fall time (0.8 to 2.0Volts) 1995 May 1 5 (26L198 and 68L198) PARAMETER PARAMETER 377 Product specification SC26C198 SC68C198 SC26L198 SC68L198 LIMITS UNIT UNIT MIN TYP MAX 10 Sclk ...
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... All voltage measurements are relative to gnd. Input and output levels are those shown in “DC Electrical Specifications”. For testing, inputs switch between 0.2 and 2.8V; outputs are measured between 0.8 and 2.0V. 6. Some values not tested, but guaranteed by design. 1995 May 1 (Continued) PARAMETER PARAMETER 2 378 Product specification SC26C198 SC68C198 SC26L198 SC68L198 LIMITS UNIT UNIT MIN TYP MAX 0 3.6864 8.0 MHz ...
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... Figure 2. Basic Write Cycle, ASYNC RWH VALID INVALID RWS Figure 3. Basic Write Cycle, SYNC 379 Product specification SC26C198 SC68C198 SC26L198 SC68L198 RWD INVALID VALID INVALID t DS DAK DAK DLY DLY C4 CEN HIGH t DH SD00194 C4 ...
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... Figure 4. Basic Read Cycle, ASYNC RWH VALID INVALID DATA= RWS t DD Figure 5. Basic Read Cycle, SYNC 380 Product specification SC26C198 SC68C198 SC26L198 SC68L198 RWD INVALID VALID INVALID DAK DLY C4 DAK DLY CEN SD00196 C4 t STP INVALID ...
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... X1 3pF 50 KOHMs TO 150 KOHMs X2 4pF TYPICAL CRYSTAL SPECIFICATION FREQUENCY: LOAD CAPACITANCE (C L TYPE OF OPERATION: Figure 7. X1/X2 Communication Crystal Clock 381 Product specification SC26C198 SC68C198 SC26L198 SC68L198 C4 INVALID VALID INVALID DAK DLY DAK DLY CEN SD00525 HIGH +5V 1K required for TTL gate. ...
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... Figure 10. Tx/Rx Clock Timing, External t RXH RxD t RXS t TXD TxD Figure 11. Transmitter and Receiver Timing In the synchronous mode extended IACKN signal cycle will start another IACKN. (This may not be desired but is allowed) 382 Product specification SC26C198 SC68C198 SC26L198 SC68L198 SD00199 TC/TO SD00200 TC/TO SD00201 SD00202 ...
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... Global RxFIFO Register, 360 Global TxFIFO Register, 360 GPOC , 361 GPOD, 361 GPOR, 361 GPOSR, 361 1995 May 1 SC26C198 SC68C198 SC26L198 SC68L198 GRxFIFO, 360 GTxFIFO, 360 H Host Interface, 339 Host interface, 339 I I/O Port Configuration Register, 360 I/O Port Interrupt and Output Register, 360 ...
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... TxFIFO, 357 TxRDY, 341 U UCIR, 359 Update CIR, 345, 359 W Wake Up Mode, 347 1995 May 1 SC26C198 SC68C198 SC26L198 SC68L198 Wake up mode, 344 Wake Up modes, 347 Wake up. Default, 347 Watch–dog Timer , 347 Watch–dog Timer Enable Register, 358 WDTRCR, 358 X XISR, 358 ...