SC26L198 Philips Semiconductors, SC26L198 Datasheet - Page 40

• Manufacturer Part Number: SC26L198
• Description: Octal UART with TTL compatibility at 3.3V and 5V supply voltages
• Manufacturer: Philips Semiconductors

1. The ASYNC pulse width low must include 4 rising edges plus the setup & hold times. For those applications where the control processor
2. Production test will use rise and fall time less than 7ns. Specified rise and fall times are guaranteed by design.
3. Sclk is required for proper bus timing. Sclk must always be faster than twice the fastest 1X data clock.
4. The meaning of DACKN is that data will be valid before the end of the C4 time.
5. All voltage measurements are relative to gnd. Input and output levels are those shown in “DC Electrical Specifications”. For testing, inputs
Philips Semiconductors
AC ELECTRICAL CHARACTERISTICS (26C198 and 68C198)
NOTES:
1995 May 1
X1 / X2 COMMUNICATION CRYSTAL CLOCK
COUNTER / TIMER BAUD RATE CLOCK (EXTERNAL CLOCK INPUT)
DACKN TIMING
I/O PORT External Clock
Gout TIMING
SYMBOL
SYMBOL
DAKdlya
DAKdlys
X1 L / H
GPOtdd
Octal UART with TTL compatibility at 3.3V
and 5V supply voltages
TC/TLH
T/RFx1
DAKdly
Tgpirtx
TC/TO
has no knowledge of the Sclk period, this will imply a CEN period of 5 Sclk rising edges.
switch between 0.2 and 2.8V; outputs are measured between 0.8 and 2.0V.
FC/T
Fx1
FIGURE
FIGURE
4
X1 clock frequency
X1 Low / High time
X1 Rise / Fall time
Clock frequency
C/T high and low time
Delay C/T clock external to output pin
DACK low from Sclk C4 rising edge
DACK high from CEN high (ASYNC)
DACK high from C4 end rising edge (SYNC)
GPI to Rx/Tx clock out
RxD setup to I/OP rising edge 1X mode
I/OP falling edge to TxD out 1X mode
GPO valid after write to GPOR
2
PARAMETER
PARAMETER
375
(Continued)
MIN
20
30
0
0
SC26C198 SC68C198
SC26L198 SC68L198
LIMITS
3.6864
TYP
TBD
TBD
TBD
TBD
28
28
10/10
MAX
8.0
60
25
40
40
8
Product specification
UNIT
UNIT
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns