SC26L198 Philips Semiconductors, SC26L198 Datasheet - Page 26

• Manufacturer Part Number: SC26L198
• Description: Octal UART with TTL compatibility at 3.3V and 5V supply voltages
• Manufacturer: Philips Semiconductors

Philips Semiconductors
Table 33. Global Interrupting Type Register
A register associated with the interrupting channel as defined in the
CIR. It contains the type of interrupt code for all interrupts.
Table 34. GRxFIFO – Global RxFIFO Register
The RxFIFO of the channel indicated in the CIR channel field.
Undefined when the CIR interrupt context is not a receiver interrupt.
Global TxFIFO Register
Table 36. IPR – Input Port Register,
This register may be read to determine the current level of the I/O
pins and examine the output of the change detectors assigned to
Table 37. I/OPIOR – I/O Port Interrupt and Output Register
I/OPIOR[7:4] bits activate the input change of state detectors. If a
pin is configured as an output, a b’1 value written to a I/O field has
no effect.
Table 38. I/OPCR – I/O Port Configuration Register
* If I/OPCR(5:4) is programmed as ’01’ then the RTSN functionality
is assigned to I/O2, otherwise, this function can be implemented on
I/O1. (This allows for a lower pin count package option)
This register contains 4, 2 bit fields that set the direction and source
for each of the I/O pins associated with the channel. The I/O2
output may be RTSN if MR1[7] is set, or may signal ”end of
transmission” if MR2[5] is set.(Please see the descriptions of these
functions under the MR1 and MR2 register descriptions) If this
control bit is cleared, the pin will use the OPR[2] as a source if
I/OPCR[5:4] is b’01. The b’00 combinations are always inputs. This
register resets to x’0, effectively configuring all I/O pins as inputs on
1995 May 1
Receiver Interrupt
0x – not receiver
10 – with receive errors
11 – w/o receive errors
0 – no change
1 – change
I/O3 enable
0 – disable
1 – enable
I/O3 control
00 – GPI/TxC input
01 – I/OPIOR[3] output
10 – TxC16x output
11 – TxC1x output
Octal UART with TTL compatibility at 3.3V
and 5V supply voltages
8 data bits of RxFIFO. MSBs set to 0 for 7, 6, 5 bit data
Bit 7
change
Bit 7
I/O3
Bits 7:6
Bit 7:6
I/O2 enable
0 – disable
1 – enable
0 – no change
1 – change
Bit 6
Bits 7:0
change
Bit 6
I/O2
Transmitter Interrupt
0 – not transmitter
1 – transmitter interrupt
I/O2 control
00 – GPI/RxC input
01 – I/OPIOR[2]/RTSN *
10 – RxC1x output
11 – RxC16x output
I/O1 enable
0 – disable
1 – enable
Bit 5
0 – no change
1 – change
Bits 5:4
Bit 5
change
Bit 7
I/O1
I/O0 enable
0 – disable
1 – enable
Bit 4
361
Reserved
read b’00
0 – no change
1 – change
I/O1 control
00 – GPI input
01 – I/OPIOR[1]/RTSN *
10 – Reserved
11 – RxC1x output
Table 35. GTxFIFO – Global TxFIFO Register
The TxFIFO of the channel indicated in the CIR channel field.
Undefined when the CIR interrupt context is not a transmitter
interrupt. Writing to the GTxFIFO when the current interrupt is not a
transmitter event may result in the characters being transmitted on a
different channel than intended.
each pin. If the change detection is not enabled or if the pin is
configured as an output, the associated change field will read b’0.
I/OPIOR[3:0] bits hold the datum which is the inverse of the datum
driven to its associated I/O pin when the I/OPCR control bits for that
pin are programmed to b’01.
power up or reset. Inputs may be used as RxC, TxC inputs or
CTSN and General Purpose Inputs simultaneously. All inputs are
equipped with change detectors that may be used to generate
interrupts or can be polled, as required.
NOTE: To ensure that CTSN, RTSN and an external RxC are
always available, if I/O2 is not selected as the RTSN output, the
RTSN function is automatically provided on I/O1.
GENERAL PURPOSE OUTPUT PIN CONTROL
The following four registers control the function of the G
These output pins have a unique control matrix which includes a
I/O3 output
OPR[3]
change
Bit 6
8 data bits of TxFIFO. MSBs not used for 7, 6, 5 bit data
I/O0
Bit 3
Bits 3:2
Bit 4:3
I/O2 output
OPR[2]
I/O3
state
The actual logic level at the I/O pin.
1 = high level; 0 =– low level.
Bit 3
Bit 2
SC26C198 SC68C198
SC26L198 SC68L198
Bits 7:0
Other types
000 – not ”other” type
001 – Change of State
010 – Address Recognition
Event
011 – Xon/Xoff status
100 – Not used
101 – Break Change
11x – do not occur
I/O2
state
I/O0 control
00 – GPI/CTSN input
01 – I/OPIOR[0]output
10 – TxC1x output
11 – TxC16x output
Bit 2
I/O1 output
OPR[1]
Bit 1
I/O1
state
Bits 1:0
Bit 2:0
Bit 1
Product specification
I/O0 output
OPR[0]
OUT
I/O0
state
Bit 0
Bit 0
0 pin.