IMP16C554 IMP Inc, IMP16C554 Datasheet - Page 6

• Manufacturer Part Number: IMP16C554
• Description: Quad Universal Asynchronous Receiver/Transmitter (UART) with FIFOs
• Manufacturer: IMP Inc

6
PROGAMMING TABLE
REGISTER FUNCTIONAL DESCRIPTIONS
TRANSMIT
REGISTER
The serial transmitter section consists of a
Transmit Hold Register (THR) and Transmit
Shift Register (TSR).The status of the transmit
hold register is provided in the Line status
Register(LSR).Writing
(THR)will transfer the contents of data
bus(D7-D0) to the Transmitter shift register is
empty. The transmit holding register empty
flag will be set to “1” when the transmitter is
empty or data is transferred to the transmit
shift register. Note that a write operation
should be performed when the transmit
holding register empty flag is set.
On the falling edge of the start bit. the receiver
internal counter will start to count 7 1/2 clocks
(16x clock) which is the center of the start bit.
The start bit is valid if the RX is still low at the
mid-bit sample of the start bit. Verifying the
start bit prevents the receiver from assembling
a false data character due to a low going
noise spike on the RX input. Receiver status
codes will be posted in the Line Status
Register.
A2
0
0
0
0
1
1
1
1
0
0
AND
A1
0
0
1
1
0
0
1
1
0
0
RECEIVE
to
this
A0
0
1
0
1
0
1
0
1
0
1
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HOLDING
register
Modem Status Register
Scratchpad Register
Line Status Register
Receive Holding
Interrupt Status
READ MODE
FIFO INTERRUPT MODE OPERATION
When the receive FIFO (FCR BIT-0=1) and
receive interrupts (IER BIT-0=1) are enabled.
receiver interrupt will occur as follows.
A)The receive data available interrupts will be
issued to the CPU when the FIFO has
reached its programmed trigger level; it will be
cleared as soon as the FIFO drops below its
programmed trigger level.
B)The ISR receive data available indication
also occurs when the FIFO trigger level is
reached, and like the interrupt it is cleared
when the FIFO dorps below the trigger level.
C)The data ready bit (LSR BIT-0) is set as
soon as a character is transferred from the
shift register to the receiver FIFO. It is reset
when the FIFO is empty.
FIFO POLLED MODE OPERATION
When FCR BIT-0=1;resetting IER BIT 3-0 to
zero puts the IMP16C554 in the FIFO polled
mode of operation. Since the receiver and
Register
Register
IMP16C554
IMP16C554
Interrupt Enable Register
Modem Control Register
FIFO Control Register
Line Control Register
MSB of Divisor Latch
Scratchpad Register
LSB of Divisor Latch
Transmit Holding
WRITE MODE
Register
© 2002 IMP, Inc.