IMP16C554 IMP Inc, IMP16C554 Datasheet - Page 8

• Manufacturer Part Number: IMP16C554
• Description: Quad Universal Asynchronous Receiver/Transmitter (UART) with FIFOs
• Manufacturer: IMP Inc

8
(stop bit=1) + (start bi=1) =4 characters.
ISR BIT-0:
0=an interrupt is pending and the ISR
contents may be used as a pointer to the
appropriate interrupt service routine.
1=no interrupt pending.
ISR BIT 1-3:
Logical combination of these bits, provides the
highest priority interrupt pending.
ISR BIT 4-7:
These bits are not used and are set to zero in
MS16C450 mode. BIT 6-7:are set to “1” in
MS16C554 mode.
FIFO CONTROL REGISTER (FCR)
This register is used to enable the FIFOs,
clear the FIFOs, set the receiver FIFO trigger
level, and select the type of DMA signaling.
0=Diosable the transmit and receive FIFO.
1=Enable the transmit and receive FIFO.
This is bit should be enabled before setting
the FIFO trigger levels.
FCR BIT-1:
0=No change.
1=Clears the contents of receive FIFO and
resets its counter logic to 0 ( the receive shift
register is not cleared or altered). This bit will
return to zero after clearing the FIFOs.
FCR BIT-2:
0=No change.
1=Clears the contents of the transmit FIFO
and resets its counter logic to 0 (the transmit
shift register is not cleared or altered). This bit
will return to zero after clearing the FIFOs.
FCR BIT-3:
0=No change.
1= Changes RXRDY and TXRDY pins from
mode “0” to mode “1”.
Transmit operation in mode “0”:
When IMP16C554 is in MS16C450 mode
(FCR bit-0=0) or in the FIFO mode (FCR
bit-0=1,FCR bit-3=0) when there are no
characters in the transmit FIFO or transmit
holding register, the TXRDY* pin will go low.
Once active the TXRDY* pin will go high
FCR BIT-0:
408-432-9100/www.impweb.com
(inactive) after the first character is loaded into
the transmit holding register.
Receive operation in mode “0”:
When IMP16C554 is in IMP16C450 mode (FCR
bit-0=0)
bit-1=1,FCR bit-3=0) and there is at least 1
character in the receive FIFO, the RXRDY*
pin will go low. Once active the RXRDY* pin
will go high (inactive) when there are no more
characters in the receiver.
Transmit operation in mode “1”:
When IMP16C554 is in IMP16C550 mode (FCR
bit-0=1,FCR bit-3=1) the TXRDY* pin will
become high (inactive) when the transmit
FIFO is completely full. It will be low if one or
more FIFO locations are empty.
Receive operation in mode “0”:
When IMP16C554 is in IMP16C550 mode (FCR
bit-0=1,FCR bit-3=1) and the trigger level or
the timeout has been reached, the RXRDY*
pin will go low. Once it is activated it will go
high (inactive) when are no more characters
in the FIFO.
FCR BIT 4-5:
Not used.
FCR BIT 6-7:
These bits are used to set the trigger level for
the receiver FIFO interrupt.
LINE CONTROL REGISTER (LCR)
The Line Control Register is used to specify
the asynchronous data communication format.
The number of the word
and parity can be selected by writing
appropriate bits in this register.
LCR BIT1-0:
These two bits specify the word length to be
transmitted or received.
BIT-7
0
0
1
1
BIT-1
0
0
1
or
IMP16C554
IMP16C554
in
BIT-6
BIT-0
0
1
0
1
0
1
0
the
FIFO trigger level
FIFO
Word length
length, stop bits,
01
04
08
14
5
6
7
mode
(FCR
© 2002 IMP, Inc.