IMP16C554 IMP Inc, IMP16C554 Datasheet - Page 9

• Manufacturer Part Number: IMP16C554
• Description: Quad Universal Asynchronous Receiver/Transmitter (UART) with FIFOs
• Manufacturer: IMP Inc

9
LCR BIT-2:
The number of stop bits can specified by this
bit.
LCR BIT-3:
Parity or no parity can be selected via this bit.
0= no parity
1=a parity bit is generated during the
transmission.
receiver also checks for received parity.
LCR BIT-4:
If the parity bit is enabled, LCR BIT-4 selects
the even or odd parity format.
0= ODD parity bit is generated by forcing an
odd number of 1`s in the transmitted data,
receiver also checks for same format.
1=EVEN parity bit is generated by forcing an
even number of 1`s in the transmitted data,
receiver also checks for same format.
LCR BIT-5:
If the parity bit is enabled, LCR BIT-5 selects
the forced parity format.
LCR BIT-5=1 and LCR BIT-4=0, parity bit is
forced to “1” in the transmitted and received
data.
LCR BIT-5=1 and LCR BIT-4=1, parity bit is
forced to “0” in the transmitted and received
data.
LCR BIT-6:
Break control bit. It causes a break condition
to be transmitted (the TX is forced to low
state).
0= normal operating condition.
1=forces the transmitter output (TX) to go low
to alert the communication terminal.
LCR BIT-7:
The internal baud rate counter latch enable
(DLAB).
0=normal operation.
1=select divisor latch register.
MODEM CONTROL REGISTER (MCR)
This register controls the interface with the
MODEM or a peripheral device (RS232).
MCR BIT-0:
BIT-2
0
1
1
1
Word length
5, 6, 7
6, 7, 8
5
1
Stop bit(s)
1-1/2
8
1
2
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0=force DTR* output to high.
1=force DTR* output to low.
MCR BIT-1:
0=force RTS* output to high.
1=force RTS* output to low.
MCR BIT-2:
No used, except in internal loop-back mode.
MCR BIT-3:
0=set the INT A-D output pin to three state
mode.
1=Enable the INT A-D output pin.
MCR BIT-4:
0=normal operation mode.
1=enable local loop-back mode (diagnostics).
The transmitter output (TX) is set high (Mark
condition), the receiver input (RX), CTS*,
DSR*, CD*, and RI* are disabled. Internally
the transmitter output is connected to the
receiver input and DTR*, RTS*, MCR* bit-2
and INT enable are connected to modem
control inputs.
In this mode, the receiver and transmitter
interrupts are fully operational. The Modem
Control interrupts are also operational. but the
interrupts sources are now the lower four bits
of the Modem Control Register instead of the
four Modem Control inputs. The interrupts are
still controlled by the IER.
MCR BIT 5-7:
Not used. Are set to zero permanently.
LINE STATUS REGISTER (LSR)
This register provides the status of data
transfer to CPU.
LSR BIT-0:
0=no data in receive holding register or FIFO.
1=data has been received and saved in the
receive holding register or FIFO.
LSR BIT-1:
0=no overrun error (normal).
1= overrun error , next character arrived
before receive holding register was emptied or
if FIFOs are enabled. an overrun error will
occur only after the FIFO is full and the next
character has been completely received in the
shift register. Note that character in the shift
register is over written, but it is not transferred
to the FIFO.
IMP16C554
IMP16C554
© 2002 IMP, Inc.