CY7C4271-10JC Cypress Semiconductor Corp, CY7C4271-10JC Datasheet - Page 3

• Manufacturer Part Number: CY7C4271-10JC
• Description: IC DEEP SYNC FIFO 32KX9 32-PLCC
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4271-10JC

• Function: Synchronous
• Memory Size: 288K (32K x 9)
• Data Rate: 100MHz
• Access Time: 8ns
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-PLCC
• Density: 256Kb
• Word Size: 9b
• Sync/async: Synchronous
• Expandable: Yes
• Package Type: LCC
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1237

Document #: 38-06015 Rev. *B
Architecture
The CY7C4261/71 consists of an array of 16K to 32K words
of nine bits each (implemented by a dual-port array of SRAM
cells), a read pointer, a write pointer, control signals (RCLK,
WCLK, REN1, REN2, WEN1, WEN2, RS), and flags (EF, PAE, PAF,
FF).
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS)
cycle. This causes the FIFO to enter the Empty condition signified by
EF being LOW. All data outputs (Q
edge of RS. In order for the FIFO to reset to its default state, a falling
edge must occur on RS and the user must not read or write while RS
is LOW. All flags are guaranteed to be valid t
LOW.
FIFO Operation
When the WEN1 signal is active LOW, WEN2 is active HIGH, and
FF is active HIGH, data present on the D
FIFO on each rising edge of the WCLK signal. Similarly, when the
REN1 and REN2 signals are active LOW and EF is active HIGH, data
in the FIFO memory will be presented on the Q
will be presented on each rising edge of RCLK while REN1 and
REN2 are active. REN1 and REN2 must set up t
for it to be a valid read function. WEN1 and WEN2 must occur t
before WCLK for it to be a valid write function.
An output enable (OE) pin is provided to three-state the Q
outputs when OE is asserted. When OE is enabled (LOW), data in
the output register will be available to the Q
devices are cascaded, the OE function will only output data on the
FIFO that is read enabled.
The FIFO contains overflow circuitry to disallow additional
writes when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q
after additional reads occur.
Write Enable 1 (WEN1). If the FIFO is configured for program-
mable flags, Write Enable 1 (WEN1) is the only write enable
control pin. In this configuration, when Write Enable 1 (WEN1)
is LOW, data can be loaded into the input register and RAM
array on the LOW-to-HIGH transition of every write clock
(WCLK). Data is stored is the RAM array sequentially and
independently of any on-going read operation.
Write Enable 2/Load (WEN2/LD). This is a dual-purpose pin.
The FIFO is configured at Reset to have programmable flags
or to have two write enables, which allows for depth
expansion. If Write Enable 2/Load (WEN2/LD) is set active
HIGH at Reset (RS = LOW), this pin operates as a second
write enable pin.
If the FIFO is configured to have two write enables, when Write
Enable (WEN1) is LOW and Write Enable 2/Load (WEN2/LD) is
HIGH, data can be loaded into the input register and RAM
Density
Package
32-pin PLCC,TQFP
CY7C4261
16K × 9
0 8
) go LOW t
0 8
0 8
LCC,PLCC,TQFP
RSF
pins is written into the
0 8
outputs after t
CY7C4271
RSF
ENS
outputs. New data
32K × 9
after RS is taken
32-pin
0 8
after the rising
before RCLK
outputs even
OE
ENS
0 8
. If
array on the LOW-to-HIGH transition of every write clock
(WCLK). Data is stored in the RAM array sequentially and
independently of any on-going read operation.
Programming
When WEN2/LD is held LOW during Reset, this pin is the load (LD)
enable for flag offset programming. In this configuration, WEN2/LD
can be used to access the four 8-bit offset registers contained in the
CY7C4261/71 for writing or reading data to these registers.
When the device is configured for programmable flags and
both WEN2/LD and WEN1 are LOW, the first LOW-to-HIGH
transition of WCLK writes data from the data inputs to the empty offset
least significant bit (LSB) register. The second, third, and fourth
LOW-to-HIGH transitions of WCLK store data in the empty offset
most significant bit (MSB) register, full offset LSB register, and full
offset MSB register, respectively, when WEN2/LD and WEN1 are
LOW. The fifth LOW-to-HIGH transition of WCLK while WEN2/LD
and WEN1 are LOW writes data to the empty LSB register again.
Figure 1 shows the registers sizes and default values for the various
device types.
It is not necessary to write to all the offset registers at one time.
A subset of the offset registers can be written; then by bringing
the WEN2/LD input HIGH, the FIFO is returned to normal read and
write operation. The next time WEN2/LD is brought LOW, a write
operation stores data in the next offset register in sequence.
The contents of the offset registers can be read to the data
outputs when WEN2/LD is LOW and both REN1 and REN2 are
LOW. LOW-to-HIGH transitions of RCLK read register
contents to the data outputs. Writes and reads should not be
performed simultaneously on the offset registers.
Programmable Flag (PAE, PAF) Operation
Whether the flag offset registers are programmed as
described in Table 1 or the default values are used, the
programmable almost-empty flag (PAE) (PAF) states are deter-
mined by their corresponding offset registers and the
difference between the read and write pointers.
8
8
8
8
Figure 1. Offset Register Location and Default Values
Empty Offset (LSB) Reg.
Default Value = 007h
Full Offset (LSB) Reg
Default Value = 007h
7
7
16K × 9
5
5
000000
(MSB)
000000
(MSB)
0
0
0
0
8
8
8
8
Empty Offset (LSB) Reg.
Default Value = 007h
Full Offset (LSB) Reg
Default Value = 007h
7
7
32K × 9
CY7C4261
CY7C4271
6
6
Page 3 of 18
0000000
0000000
(MSB)
(MSB)
0
0
0
0