CY7C4271-10JC Cypress Semiconductor Corp, CY7C4271-10JC Datasheet - Page 8

• Manufacturer Part Number: CY7C4271-10JC
• Description: IC DEEP SYNC FIFO 32KX9 32-PLCC
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4271-10JC

• Function: Synchronous
• Memory Size: 288K (32K x 9)
• Data Rate: 100MHz
• Access Time: 8ns
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-PLCC
• Density: 256Kb
• Word Size: 9b
• Sync/async: Synchronous
• Expandable: Yes
• Package Type: LCC
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1237

Document #: 38-06015 Rev. *B
Switching Waveforms
Notes:
14. t
15. t
REN1, REN2
Read Cycle Timing
REN1, REN2
Write Cycle Timing
edge of RCLK and the rising edge of WCLK is less than t
edge of WCLK and the rising edge of RCLK is less than t
(if applicable)
SKEW1
SKEW1
Q
D
WEN2
0
0
WEN1
WCLK
WEN1
WEN2
WCLK
RCLK
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between the rising
RCLK
–D
–Q
OE
EF
FF
17
17
t
ENS
t
OLZ
t
SKEW1
t
ENH
t
t
CLKH
CLKH
[14]
t
t
t
WFF
A
REF
t
SKEW1
SKEW2
OE
, then FF may not change state until the next WCLK rising edge.
, then EF may not change state until the next RCLK rising edge.
t
t
CLK
CKL
t
SKEW1
NO OPERATION
[15]
t
DS
t
t
CLKL
CLKL
t
ENS
t
VALID DATA
DH
t
ENH
t
REF
t
WFF
t
OHZ
NO OPERATION
NO OPERATION
CY7C4261
CY7C4271
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