74LVC1G74DC,125 NXP Semiconductors, 74LVC1G74DC,125 Datasheet - Page 14

• Manufacturer Part Number: 74LVC1G74DC,125
• Description: IC SNGL D FF POS-EDG TRIG 8VSSOP
• Manufacturer: NXP Semiconductors
• Series: 74LVCr
• Type: D-Typer

Specifications of 74LVC1G74DC,125

• Output Type: Differential
• Package / Case: US8, 8-VSSOP
• Function: Set(Preset) and Reset
• Number Of Elements: 1
• Number Of Bits Per Element: 1
• Frequency - Clock: 200MHz
• Trigger Type: Positive Edge
• Current - Output High, Low: 32mA, 32mA
• Voltage - Supply: 1.65 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Circuits: 1
• Logic Family: 74LVC
• Logic Type: CMOS
• Polarity: Inverting/Non-Inverting
• Input Type: Single-Ended
• Propagation Delay Time: 13.4 ns
• High Level Output Current: - 32 mA
• Low Level Output Current: 32 mA
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Voltage (min): 1.65 V
• Technology: CMOS
• Number Of Bits: 1
• Number Of Elements: 1
• Clock-edge Trigger Type: Positive-Edge
• Operating Supply Voltage (typ): 1.8/2.5/3.3/5V
• Package Type: VSSOP
• Operating Supply Voltage (min): 1.65V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Delay Time - Propagation: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4494-2; 74LVC1G74DC-G; 74LVC1G74DC-G; 935274973125

NXP Semiconductors
13. Package outline
Fig 11. Package outline SOT505-2 (TSSOP8)
74LVC1G74
Product data sheet
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
UNIT
mm
VERSION
OUTLINE
SOT505-2
max.
1.1
A
0.15
0.00
A 1
8
1
0.95
0.75
A 2
y
pin 1 index
IEC
e
Z
0.25
A 3
D
0.38
0.22
b p
b p
All information provided in this document is subject to legal disclaimers.
0
5
0.18
0.08
4
JEDEC
c
- - -
w
REFERENCES
D
3.1
2.9
M
(1)
Single D-type flip-flop with set and reset; positive edge trigger
Rev. 9 — 5 August 2010
E
3.1
2.9
(1)
c
JEITA
scale
0.65
2.5
e
A
H E
4.1
3.9
A 2
A 1
0.5
L
H E
E
5 mm
0.47
0.33
detail X
L p
0.2
v
L
L p
PROJECTION
EUROPEAN
0.13
w
A
(A 3 )
74LVC1G74
0.1
y
X
v
θ
M
0.70
0.35
Z
© NXP B.V. 2010. All rights reserved.
A
(1)
ISSUE DATE
02-01-16
8°
0°
θ
SOT505-2
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