st10f269z1 STMicroelectronics, st10f269z1 Datasheet - Page 112

• Manufacturer Part Number: st10f269z1
• Description: St10f269 16-bit Mcu With Mac Unit, 256k Byte Flash Memory And 12k Byte Ram
• Manufacturer: STMicroelectronics

17 - WATCHDOG TIMER
17 - WATCHDOG TIMER
The Watchdog Timer is a fail-safe mechanism
which
malfunctioning for long periods of time.
The Watchdog Timer is always enabled after a
reset of the chip and can only be disabled in the
time interval until the EINIT (end of initialization)
instruction has been executed.
Therefore, the chip start-up procedure is always
monitored. The software must be designed to
service the watchdog timer before it overflows. If,
WDTCON (FFAEh / D7h)
Notes: 1. More than one reset indication flag may be set. After EINIT, all flags are cleared.
112/184
WDTIN
WDTR
SWR
SHWR
LHWR
PONR
15
1-3
2. Power-on is detected when a rising edge from V
3. These bits cannot be directly modified by software.
1- 2-3
1-3
1-3
1-3
14
prevents
13
Watchdog Timer Input Frequency Selection
‘0’: Input Frequency is f
‘1’: Input Frequency is f
Watchdog Timer Reset Indication Flag
Set by the watchdog timer on an overflow.
Cleared by a hardware reset or by the SRVWDT instruction.
Software Reset Indication Flag
Set by the SRST execution.
Cleared by the EINIT instruction.
Short Hardware Reset Indication Flag
Set by the input RSTIN.
Cleared by the EINIT instruction.
Long Hardware Reset Indication Flag
Set by the input RSTIN.
Cleared by the EINIT instruction.
Power-On (Asynchronous) Reset Indication Flag
Set by the input RSTIN if a power-on condition has been detected.
Cleared by the EINIT instruction.
WDTREL
12
RW
the
11
microcontroller
10
9
CPU
CPU
8
/2.
/128.
DD
from
= 0 V to V
7
-
SFR
DD
6
-
due to hardware or software related failures, the
software fails to do so, the watchdog timer
overflows and generates an internal hardware
reset. It pulls the RSTOUT pin low in order to allow
external hardware components to be reset.
Each of the different reset sources is indicated in
the WDTCON register.
The indicated bits are cleared with the EINIT
instruction. The origin of the reset can be
identified during the initialization phase.
> 2.0 V is recognized on the internal 3.3V supply.
PONR LHWR SHWR
HR
5
HR
4
HR
3
SWR
HR
Reset Value: 00xxh
2
WDTR WDTIN
HR
ST10F269
1
RW
0