pck2002 NXP Semiconductors, pck2002 Datasheet

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pck2002

Manufacturer Part Number
pck2002
Description
0-300 Mhz I2c 1 18 Clock Buffer
Manufacturer
NXP Semiconductors
Datasheet

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Semiconductors
Product data
File under Integrated Circuits ICL03
hilips
PCK2002
0–300 MHz I
2
C 1:18 clock buffer
INTEGRATED CIRCUITS
2001 Jul 19

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pck2002 Summary of contents

Page 1

... PCK2002 2 0–300 MHz I Product data File under Integrated Circuits ICL03 hilips Semiconductors INTEGRATED CIRCUITS C 1:18 clock buffer 2001 Jul 19 ...

Page 2

... Spread spectrum compliant Individual clock output enable/disable via I DESCRIPTION The PCK2002 is a 1–18 fanout buffer used for 133/100 MHz CPU, 66/33 MHz PCI, 14.318 MHz REF, or 133/100/66 MHz SDRAM clock distribution. 18 outputs are typically used to support SDRAM DIMMS commonly found in desktop, workstation or server applications. All clock outputs meet Intel’ ...

Page 3

... I Note 2 V > < Note 2 V > For temperature range +70 C above +55 C derate linearly with 11.3mW/K CONDITIONS CONDITIONS 3 Product data PCK2002 BUF_OUTn LIMITS UNIT UNIT MIN MAX –0.5 +4.6 V –50 mA –0.5 +4 – ...

Page 4

... GND I DD 3.135 to 3.465 – 0. TEST CONDITIONS NOTES Measured at 1 0.4 V and Product data PCK2002 LIMITS +70 C UNIT amb MIN MAX 2 0 – 0.3 0 – 0.1 — 2.4 — ...

Page 5

... I C has been chosen as the serial bus interface to control the PCK2002. I Unbuffered SDRAM DIMM. All vendors are required to determine the legal issues associated with the manufacture Address assignment: The clock driver in this specification uses the single, 7-bit address shown below. All devices can use the address if only one master clock driver is used in a design ...

Page 6

... Assume that the board designer will use a single external pull-up resistor for 2 range. Assume one I C device per DIMM (serial presence detect), one circuitry must be characterized and in the data sheet Peripherals Data Handbook IC12 (1997). 6 Product data PCK2002 controller, one ...

Page 7

... Clock Output Disable Low Clock Output Disable Low Clock Output Disable Low Clock Output Disable Low Clock Output Disable Low Clock Output Disable Low 7 Product data PCK2002 BIT CONTROL 1 Active Active Active Active Active Active Active Active BIT CONTROL 1 Active Active ...

Page 8

... At power up all SDRAM outputs are enabled and active. Program all reserved bits to “0”. 2001 Jul 19 CONTROL FUNCTION CONTROL FUNCTION 0 Clock Output Disable Low Clock Output Disable Low (Reserved) — (Reserved) — (Reserved) — (Reserved) — (Reserved) — (Reserved) — 8 Product data PCK2002 BIT CONTROL 1 Active Active — — — — — — ...

Page 9

... Figure 3. Buffer Output clock 2001 Jul 19 TEST CIRCUIT PULSE GENERATOR V M SW00246 V DD Figure 4. Load circuitry for switching times t PZL PZH V M outputs enabled SW00245 SW00247 9 Product data PCK2002 Open V SS 500 D.U.T. 500 TEST ...

Page 10

... Philips Semiconductors 2 0–300 MHz I C 1:18 clock buffer TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm 2001 Jul 19 10 Product data PCK2002 SOT362-1 ...

Page 11

... Philips Semiconductors 2 0–300 MHz I C 1:18 clock buffer SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm 2001 Jul 19 11 Product data PCK2002 SOT370-1 ...

Page 12

... Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 hilips Semiconductors 2001 Jul 19 Copyright Philips Electronics North America Corporation 2001 All rights reserved. Printed in U.S.A. Document order number: 12 Product data PCK2002 Date of release: 07-01 9397 750 08585 ...

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