pck2002 NXP Semiconductors, pck2002 Datasheet - Page 2

• Manufacturer Part Number: pck2002
• Description: 0-300 Mhz I2c 1 18 Clock Buffer
• Manufacturer: NXP Semiconductors

FEATURES
QUICK REFERENCE DATA
ORDERING INFORMATION
PIN CONFIGURATION
I
2
Philips Semiconductors
2001 Jul 19
C is a trademark of Philips Semiconductors Corporation.
HIGH speed, LOW noise non-inverting 1–18 buffer
Typically used to support four SDRAM DIMMs
Multiple V
3.3 V operation
Separate 3-State pin for testing
ESD protection exceeds 2000 V per Standard 801.2
Optimized for 66 MHz, 100 MHz and 133 MHz operation
Typical 175 ps skew outputs
Available in 48-pin SSOP and TSSOP packages
See PCK2002M for mobile (reduced pincount) 28-pin 1-10 buffer
version
0–300 MHz I
SYMBOL
t
t
I
48-Pin Plastic TSSOP
PLH
PHL
CC
48-Pin Plastic SSOP
t
t
r
f
PACKAGES
DD
, V
BUF_OUT16
RESERVED
RESERVED
BUF_OUT0
BUF_OUT1
BUF_OUT2
BUF_OUT3
BUF_OUT4
BUF_OUT5
BUF_OUT6
BUF_OUT7
SS
Propagation delay
BUF_IN to BUF_OUT
Rise time
Fall time
Total supply current
BUF_IN
V
pins for noise reduction
V
V
V
V
V
DDI2C
V
V
V
V
V
SDA
DD0
DD2
DD1
DD3
SS0
SS1
SS2
DD4
SS3
SS4
2
10
11
12
14
15
16
17
18
19
13
20
21
22
23
24
1
2
3
4
5
6
7
8
9
C 1:18 clock buffer
PARAMETER
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SW00731
n
RESERVED
RESERVED
V
BUF_OUT15
BUF_OUT14
V
V
BUF_OUT13
BUF_OUT12
V
OE
V
BUF_OUT11
BUF_OUT10
V
V
BUF_OUT9
BUF_OUT8
V
V
BUF_OUT17
V
V
SCL
TEMPERATURE RANGE
DD9
SS9
DD8
SS8
DD7
SS7
DD6
SS6
DD5
SS5
SSI2C
0 to +70 C
0 to +70 C
V
V
V
V
CC
CC
CC
CC
= 3.3 V, CL = 30 pF
= 3.3 V, CL = 30 pF
= 3.3 V, CL = 30 pF
= 3.465 V
2
All clock outputs meet Intel’s drive, rise/fall time, accuracy, and skew
DESCRIPTION
The PCK2002 is a 1–18 fanout buffer used for 133/100 MHz CPU,
66/33 MHz PCI, 14.318 MHz REF, or 133/100/66 MHz SDRAM
clock distribution. 18 outputs are typically used to support up to
4 SDRAM DIMMS commonly found in desktop, workstation or
server applications.
requirements. An I
enabled/disabled individually. An output disabled via the I
interface will be held in the LOW state. In addition, there is an OE
input which 3-States all outputs.
PIN DESCRIPTION
3, 7, 12, 16,
13, 14, 17, 18
1, 2, 47, 48
31, 32, 35,
40, 41, 44,
20, 29, 33,
27, 30, 34,
NUMBER
37, 42, 46
Spread spectrum compliant
Individual clock output enable/disable via I
6, 10, 15,
4, 5, 8, 9
19, 22,
21, 28
39, 43
PIN
36
45
38
24
25
23
26
11
CONDITIONS
ORDER CODE
PCK2002DGG
PCK2002DL
Output
Output
Output
Output
Output
TYPE
Input
Input
Input
Input
Input
Input
Input
I/O
I/O
n/a
2
C interface is included to allow each output to be
BUF_OUT (0–3)
BUF_OUT (4–7)
RESERVED
BUF_OUT
BUF_OUT
BUF_OUT
SYMBOL
V
V
BUF_IN
(12–15)
(16–17)
V
V
(8–11)
DD (0–9)
SS (0–9)
SDA
SCL
DDI2C
SSI2C
OE
DRAWING NUMBER
TYPICAL
Buffered clock outputs
Buffered clock outputs
Buffered clock outputs
Buffered clock outputs
Buffered clock outputs
Buffered clock input
Active high output
enable
I
I
3.3 V Power supply
Ground
3.3 V I
supply
I
Undefined
2
2
2
2
C
C serial data
C serial clock
C Ground
2.7
2.9
1.1
1.0
35
SOT362-1
SOT370-1
PCK2002
FUNCTION
853-2267 26745
2
C Power
Product data
2
C
UNIT
ns
ns
ns
A