pck2002 NXP Semiconductors, pck2002 Datasheet - Page 5

• Manufacturer Part Number: pck2002
• Description: 0-300 Mhz I2c 1 18 Clock Buffer
• Manufacturer: NXP Semiconductors

2) Options: It is our understanding that metal mask options and other pinouts of this type of clock driver will be allowed to use the same address
Philips Semiconductors
I
I
Unbuffered SDRAM DIMM. All vendors are required to determine the legal issues associated with the manufacture of I
1) Address assignment: The clock driver in this specification uses the single, 7-bit address shown below. All devices can use the address if only
one master clock driver is used in a design. The address can be re-used for the CKBF device if no other conflicting I
the system.
The following address was confirmed by Philips on 09/04/96.
NOTE: The R/W bit is used by the I
indicates a request for data (READ) from the clock driver. Since the definition of the clock buffer only allows the controller to WRITE data; the
R/W bit of the address will always be seen as ‘zero’. Optimal address decoding of this bit is left to the vendor.
as the original CKBF device. I
3) Slave/Receiver: The clock driver is assumed to require only slave/receiver functionality. Slave/transmitter functionality is optional.
4) Data Transfer Rate: 100 kbits/s (standard mode) is the base functionality required. Fast mode (400 kbits/s) functionality is optional.
5) Logic Levels: I
based on a 3.3 Volt supply.
6) Data Byte Format: Byte format is 8 Bits as described in the following appendices.
7) Data Protocol: To simplify the clock I
The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been
transferred. Indexed bytes are not allowed. However, the SMBus controller has a more specific format than the generic I
The clock driver must meet this protocol which is more rigorous than previously stated I
controller. The controller “writes” to the clock driver and if possible would “read” from the clock driver (the clock driver is a slave/receiver only
and is incapable of this transaction.)
“The block write begins with a slave address and a write condition. After the command code the host (controller) issues a byte count which
describes how many more bytes will follow in the message. If the host had 20 bytes to send, the first byte would be the number 20 (14h),
followed by the 20 bytes of data. The byte count may not be 0. A block write command is allowed to transfer a maximum of 32 data bytes.”
NOTE: The acknowledgement bit is returned by the slave/receiver (the clock driver).
2001 Jul 19
2
2
A6
1
C has been chosen as the serial bus interface to control the PCK2002. I
C CONSIDERATIONS
0–300 MHz I
A5
1
2
C logic levels are based on a percentage of V
A4
0
2
A3
1
C 1:18 clock buffer
2
C addresses are defined in terms of function (master clock driver) rather than form (pinout, and option).
1 bit
Ack
Start bit
A2
0
2
1 bit
C controller as a data direction bit. A ‘zero’ indicates a transmission (WRITE) to the clock device. A ‘one’
2
C interface, the clock driver serial protocol was specified to use only block writes from the controller.
Data Byte 1
8 bits
A1
0
Slave Address
7 bits
A0
1
Ack
1
R/W
Data Byte 2
R/W
0
1
8 bits
DD
Ack
for the controller and other devices on the bus. Assume all devices are
1
5
Command Code
2
Ack
C was chosen to support the JEDEC proposal JC-42.5 168 Pin
1
8 bits
...
2
Ack
Data Byte 2
C protocol. Treat the description from the viewpoint of
1
8 bits
Byte Count = N
Ack
1
Stop
1
SW00279
2
C clock driver is used in
2
C devices.
2
C protocol.
PCK2002
Product data