dsp56853 Freescale Semiconductor, Inc, dsp56853 Datasheet - Page 20

• Manufacturer Part Number: dsp56853
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

20
Pin No.
Table 3-1. 56853 Signal and Package Information for the 128-pin LQFP (Continued)
24
25
33
1
2
3
4
Signal Name
GPIOF0
GPIOF1
GPIOF2
GPIOF3
EXTAL
CLKO
MISO
MOSI
XTAL
SCK
SS
Input/Output (Z)
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Output
Type
Input
Input
56853 Technical Data, Rev. 6
SPI Master In/Slave Out (MISO)—This serial data pin is an input to a
master device and an output from a slave device. The MISO line of a
slave device is placed in the high-impedance state if the slave device
is not selected. The driver on this pin can be configured as an
open-drain driver by the SPI’s Wired-OR mode (WOM) bit when this
pin is configured for SPI operation.
Port F GPIO (0)—This pin is a General Purpose I/O (GPIO) pin that
can be individually programmed as input or output pin.
SPI Master Out/Slave In (MOSI)—This serial data pin is an output
from a master device and an input to a slave device. The master
device places data on the MOSI line a half-cycle before the clock
edge that the slave device uses to latch the data. The driver on this
pin can be configured as an open-drain driver by the SPI’s WOM bit
when this pin is configured for SPI operation.
Port F GPIO (1)—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.
SPI Serial Clock (SCK)—This bidirectional pin provides a serial bit
rate clock for the SPI. This gated clock signal is an input to a slave
device and is generated as an output by a master device. Slave
devices ignore the SCK signal unless the SS pin is active low. In both
master and slave SPI devices, data is shifted on one edge of the SCK
signal and is sampled on the opposite edge, where data is stable. The
driver on this pin can be configured as an open-drain driver by the
SPI’s WOM bit when this pin is configured for SPI operation. When
using Wired-OR mode, the user must provide an external pull-up
device.
Port F GPIO (2)—This pin is a General Purpose I/O (GPIO) pin that
can be individually programmed as input or output pin.
SPI Slave Select (SS)—This input pin selects a slave device before a
master device can exchange data with the slave device. SS must be
low before data transactions and must stay low for the duration of the
transaction. The SS line of the master must be held high.
Port F GPIO (3)—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.
Crystal Oscillator Output (XTAL)—This output connects the internal
crystal oscillator output to an external crystal. If an external clock
source other than a crystal oscillator is used, XTAL must be used as
the input.
External Crystal Oscillator Input (EXTAL)—This input should be
connected to an external crystal. If an external clock source other
than a crystal oscillator is used, EXTAL must be tied off. See
4.5.2
Clock Output (CLKO)—This pin outputs a buffered clock signal.
When enabled, this signal is the system clock divided by four.
Description
Freescale Semiconductor
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