dsp56853 Freescale Semiconductor, Inc, dsp56853 Datasheet - Page 31

• Manufacturer Part Number: dsp56853
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

4.6 External Memory Interface Timing
The External Memory Interface is designed to access static memory and peripheral devices.
sample timing and parameters that are detailed in
The timing of each parameter consists of both a fixed delay portion and a clock related portion; as well as user
controlled wait states. The equation:
Some of the parameters contain two sets of numbers. These parameters have two different paths and clock edges
that must be considered. Check both sets of numbers and use the smaller result. The appropriate entry may change
if the operating frequency of the part changes.
The timing of write cycles is different when WWS = 0 than when WWS > 0. Therefore, some parameters contain
two sets of numbers to account for this difference. The “Wait States Configuration” column of
used to make the appropriate selection.
Freescale Semiconductor
should be used to determine the actual time of each parameter. The terms in the above equation are defined as:
Operating Conditions: V
External reference crystal frequency for the PLL
PLL output frequency
PLL stabilization time
1.
The PLL is optimized for 4MHz input crystal.
2.
t
D fixed portion of the delay, due to on-chip path delays.
P
M Fixed portion of a clock period inherent in the design. This number is adjusted to account for possible
W the sum of the applicable wait state controls. See the “Wait State Controls” column of
An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly.
This is the minimum time required after the PLL setup is changed to ensure reliable operation.
parameter delay time
the period of the system clock, which determines the execution rate of the part (i.e. when the device is
operating at 120 MHz, P = 8.33 ns).
clock duty cycle derating.
the applicable controls for each parameter. See the EMI chapter of the 83x Peripheral Manual for
details of what each wait state field controls.
t = D + P * (M + W)
Characteristic
SS
= V
2
SSIO
= V
SSA
= 0 V, V
DD
Table 4-6 PLL Timing
56853 Technical Data, Rev. 6
= 1.62-1.98V, V
1
Table
Symbol
DDIO
4-7.
f
t
f
osc
plls
clk
= V
DDA
= 3.0–3.6V, T
Min
40
—
2
A
= –40° to +120°C, C
Typ
—
4
1
External Memory Interface Timing
Max
240
L
10
4
≤ 50pF, f
Table 4-7
Figure 4-10
op
Table 4-7
= 120MHz
Unit
MHz
MHz
ms
should be
shows
for
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