dsp56853 Freescale Semiconductor, Inc, dsp56853 Datasheet - Page 21

• Manufacturer Part Number: dsp56853
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
Pin No.
Table 3-1. 56853 Signal and Package Information for the 128-pin LQFP (Continued)
54
52
51
53
50
49
Signal Name
TRST
TDO
TMS
TCK
TDI
DE
Input/Output
Output (Z)
Type
Input
Input
Input
Input
56853 Technical Data, Rev. 6
Test Clock Input (TCK)—This input pin provides a gated clock to
synchronize the test logic and to shift serial data to the
JTAG/Enhanced OnCE port. The pin is connected internally to a
pull-down resistor.
Test Data Input (TDI)—This input pin provides a serial input data
stream to the JTAG/Enhanced OnCE port. It is sampled on the rising
edge of TCK and has an on-chip pull-up resistor.
Test Data Output (TDO)—This tri-statable output pin provides a
serial output data stream from the JTAG/Enhanced OnCE port. It is
driven in the Shift-IR and Shift-DR controller states, and changes on
the falling edge of TCK.
Test Mode Select Input (TMS)—This input pin is used to sequence
the JTAG TAP controller’s state machine. It is sampled on the rising
edge of TCK and has an on-chip pull-up resistor.
Note:
Test Reset (TRST)—As an input, a low signal on this pin provides a
reset signal to the JTAG TAP controller. To ensure complete
hardware reset, TRST should be asserted whenever RESET is
asserted. The only exception occurs in a debugging environment,
since the Enhanced OnCE/JTAG module is under the control of the
debugger. In this case it is not necessary to assert TRST when
asserting RESET. Outside of a debugging environment RESET
should be permanently asserted by grounding the signal, thus
disabling the Enhanced OnCE/JTAG module on the controller.
Note:
is to be used in a debugging environment, TRST may be tied to V
a 1K resistor.
Debug Event (DE)—This is an open-drain, bidirectional, active low
signal. As an input, it is a means of entering debug mode of operation
from an external command controller. As an output, it is a means of
acknowledging that the chip has entered debug mode.
This pin is connected internally to a weak pull-up resistor.
Always tie the TMS pin to V
For normal operation, connect TRST directly to V
Description
DD
through a 2.2K resistor.
SS
. If the design
SS
Introduction
through
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