dsp56004 Freescale Semiconductor, Inc, dsp56004 Datasheet - Page 18

• Manufacturer Part Number: dsp56004
• Description: Symphonytm Audio Dsp Family 24-bit Digital Signal Processors
• Manufacturer: Freescale Semiconductor, Inc

Signal/Connection Descriptions
Serial Host Interface (SHI)
1-12
SS
HA2
HREQ
Signal Name
Table 1-8 Serial Host Interface (SHI) signals (Continued)
Input or
Output
Signal
Input
Input
Type
Freescale Semiconductor, Inc.
Tri-stated
Tri-stated
For More Information On This Product,
during
Reset
State
DSP56004/D, Rev. 3
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SPI Slave Select (SS)—This signal is an active low
Schmitt-trigger input when configured for the SPI
mode. When configured for the SPI Slave mode, this
signal is used to enable the SPI slave for transfer.
When configured for the SPI Master mode, this
signal should be kept deasserted. If it is asserted
while configured as SPI master, a bus error
condition will be flagged.
I
Schmitt-trigger input when configured for the I
mode. When configured for the I
HA2 signal is used to form the slave device address.
HA2 is ignored in the I
deasserted, the SHI ignores SCK clocks and keeps
the MISO output signal in the high-impedance
state.
Note:
Host Request—This signal is an active low Schmitt-
trigger input when configured for the Master mode, but
an active low output when configured for the Slave
mode. When configured for the Slave mode, HREQ is
asserted to indicate that the SHI is ready for the next data
word transfer and deasserted at the first clock pulse of
the new data word transfer. When configured for the
Master mode, HREQ is an input and when asserted by
the external slave device, it will trigger the start of the
data word transfer by the master. After finishing the data
word transfer, the master will await the next assertion of
HREQ to proceed to the next transfer.
Note:
2
C Slave Address 2 (HA2)—This signal uses a
This signal is tri-stated during hardware reset,
software reset, or individual reset (no need for
external pull-up in this state).
This signal is tri-stated during hardware, software,
individual reset, or when the HREQ[1:0] bits (in the
HCSR) are cleared (no need for external pull-up in this
state).
Signal Description
2
C Master mode. If SS is
2
C Slave mode, the
MOTOROLA
2
C