dsp56004 Freescale Semiconductor, Inc, dsp56004 Datasheet - Page 55

• Manufacturer Part Number: dsp56004
• Description: Symphonytm Audio Dsp Family 24-bit Digital Signal Processors
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
C
R
Bus Load
L
P
Table 2-14 Considerations for Programming the SHI Clock control Register (HCKR)
= 50 pF,
= 2 k
The Programmed Serial Clock Cycle, t
HDM0 and HRS bits of the HCKR (SHI Clock control Register).
The expression for t
where
In I
The DSP56004 provides an improved I
100 kHz I
kHz. The actual maximum frequency is limited by the bus capacitances (C
up resistors (R
below)), and by the input filters.
Consideration for programming the SHI Clock Control Register (HCKR) – Clock
Divide Ratio: the master must generate a bus free time greater than T172 slave when
operating with a DSP56004 SHI I
The table below describes a few examples
2
•
•
•
81 MHz 81 MHz
C mode, you may select a value for the Programmed Serial Clock Cycle from
Master
Oper-
ating
Freq.
HRS is the Prescaler Rate Select bit. When HRS is cleared, the fixed divide-by-
eight prescaler is operational. When HRS is set, the prescaler is bypassed.
HDM5–HDM0 are the Divider Modulus Select bits.
A divide ratio from 1 to 64 (HDM5–HDM0 = 0 to $3F) may be selected.
6
1024
Conditions to be Considered
2
Freescale Semiconductor, Inc.
C bus protocol, the SHI in I
T
C
For More Information On This Product,
t
Oper-
P
Slave
T
ating
Freq.
I
2
), (which affect the rise and fall time of SDA and SCL, (see table
C
CCP
=
I
2
Go to: www.freescale.com
CCP
(HDM5–HDM0 = 2, HRS = 1)
(HDM5–HDM0 = $3F, HRS = 0).
Tc 2
Bypassed
Narrow
Master
Mode
Filter
Wide
is:
DSP56004/D, Rev. 3
HDM[5:0]
2
C slave.
Bypassed
Narrow
Mode
Slave
Filter
Wide
2
I
+
2
C mode supports data transfers at up to 1000
2
CCP
C bus protocol. In addition to supporting the
1
Serial Host Interface (SHI) I
:
, is specified by the value of the HDM5–
Slave
7
36 ns
60 ns
95 ns
T172
1 HRS
–
56
62
52
issible
Perm-
t
Min.
I
2
CCP
+
to
T
T
T
1
Resulting Limitations
C
C
C
Master
103 ns
41 ns
66 ns
T172
2
C Protocol Timing
Specifications
Maximum
Frequency
I
1010 kHz
2
825 kHz
634 kHz
C Serial
L
),the pull-
2-31