isp1160 NXP Semiconductors, isp1160 Datasheet - Page 61

• Manufacturer Part Number: isp1160
• Description: Isp1160 Embedded Universal Serial Bus Host Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 44:
9397 750 13963
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Hc PInterruptEnable register: bit allocation
reserved
R/W
R/W
15
0
7
0
10.4.5 Hc PInterruptEnable register (R/W: 25H/A5H)
ClkReady
Table 43:
The bits 6:0 in this register are the same as those in the Hc PInterrupt register. They
are used together with bit 0 of the HcHardwareConfiguration register to enable or
disable the bits in the Hc PInterrupt register.
On power-on, all bits in this register are masked with logic 0. This means no interrupt
request output on the interrupt pin INT can be generated.
When the bit is set to logic 1, the interrupt for the bit is not masked but enabled.
Code (Hex): 25 — read
Code (Hex): A5 — write
Bit
2
1
0
R/W
R/W
14
0
6
0
Hc PInterrupt register: bit description
Suspended
Symbol
AllEOT
Interrupt
ATLInt
SOFITLInt
Enable
R/W
R/W
HC
13
0
5
0
Rev. 05 — 24 December 2004
Description
0 — no event
1 — implies that data transfer has been completed via PIO transfer
or DMA transfer. Occurrence of internal or external EOT will set
this bit.
0 — no event
1 — implies that the microprocessor must read ATL data from the
HC. This requires that the HcBufferStatus register must first be
read. The time for this interrupt depends on the number of clocks
bit set for USB activities in each ms.
0 — no event
1 — implies that SOF indicates the 1 ms mark. The ITL buffer that
the HC has handled must be read. To know the ITL buffer status,
the HcBufferStatus register must first be read. This is for the
microprocessor to get ISO data to or from the HC. For more
information, see the 6th paragraph in
Interrupt
Enable
OPR
R/W
R/W
12
0
4
0
reserved
reserved
R/W
R/W
11
0
3
0
…continued
Interrupt
Enable
Embedded USB Host Controller
EOT
R/W
R/W
10
0
2
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Section
Interrupt
Enable
R/W
R/W
ATL
9.5.
9
0
1
0
ISP1160
Interrupt
Enable
SOF
R/W
R/W
8
0
0
0
61 of 88