mc33789 Freescale Semiconductor, Inc, mc33789 Datasheet - Page 66

• Manufacturer Part Number: mc33789
• Description: Airbag System Basis Chip Sbc With Power Supply And Psi5 Sensor Interface
• Manufacturer: Freescale Semiconductor, Inc

Table 35. Operational Mode SPI Command Table
Table 36. SPI Command, - Test Mode Entry
FUNCTIONAL DEVICE OPERATION
SENSOR MESSAGE, OPERATION COMMAND AND SPI
Operational Mode SPI Command Table
summarized in
TEST-MODE SPI COMMANDS
high, i.e. 5.0 V, and the test-mode entry command is
received.
FAILURE MODE REQUIREMENTS
SPI Error
format is incorrect.
an error response message on SO with the 'SPI Error' (SE)
66
33789
ADD
0A
0B
0C
0D
0E
1A
1B
1C
1D
1E
00
01
02
03
04
05
06
07
08
09
0F
10
11
12
13
14
15
16
17
18
19
1F
R
TEST
All of the 33789 operational mode SPI commands are
The 33789 enters Test mode when the PPT pin is driven
SPI Error is defined as a condition where the SPI frame
When a SPI error is detected, the 33789 will respond with
DCS_CONTROL
SYNC_ENABLE
PS_CONTROL
LINE_ENABLE
SCRAP_SEED
WDOG_FEED
AI_CONTROL
WDOG_TEST
LIN_CONFIG
SCRAP_KEY
LINE_MODE
SAFE_TH_0
SAFE_TH_1
SAFE_TH_2
SAFE_TH_3
SAFE_TH_4
SAFE_TH_5
SAFE_TH_6
SAFE_TH_7
T_UNLOCK
ESR_DIAG
DIAG_CLR
SAFE_CTL
OUT1_CTL
OUT2_CTL
Command
STATUS
NOP
SO
SI
Table
Satellite Synchronization Select R/W
Scrapping Function Key Submit
Enable ESR Test / Read VER-
General Purpose Driver1 Out-
General Purpose Driver2 Out-
Satellite Channel Sync Pulse
Energy Reserve Activation
ARM/DISARM Output and
15
Scrapping Function Seed
Safing Threshold 0 Value
Safing Threshold 1 Value
Safing Threshold 2 Value
Safing Threshold 3 Value
Safing Threshold 4 Value
Safing Threshold 5 Value
Safing Threshold 6 Value
Safing Threshold 7 Value
Watchdog Pet Command
Satellite Channel Enable
Safing Threshold Unlock
Analog Interface Control
1
0
Diagnostic Test Clear
35.
DC Sensor Control
LIN Configuration
Watchdog Test
33789 Status
Mode Control
put Control
put Control
Function
Request
Control
Enable
No-Op
DIAC
14
1
1
13
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
12
1
0
W
W
W
W
W
W
R
R
TESTMODE (ADDR=0xD5, DATA=0x52)
15:0
4A
4B
4C
4D
4E
4F
5A
5B
5C
5D
5E
5F
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
8
11
0
1
SS3
DC5 DC4 DC3
DC5 DC4 DC3
U7
D7
T7
T7
T7
T7
T7
T7
T7
T7
K7
X
7
x
x
x
x
x
x
x
x
x
x
x
x
Operational Mode SPI Commands
SS2
10
T6
T6
T6
T6
T6
T6
T6
T6
U6
D6
K6
1
1
6
X
x
x
x
x
x
x
x
x
x
x
x
x
REN RX0
SS1
U5
D5
SC
T5
T5
T5
T5
T5
T5
T5
T5
K5
X
5
x
x
x
x
x
x
x
x
x
x
Write Data
9
0
1
AIC4 AIC3 AIC2 AIC1 AIC0
BOE
SS0
DC2 DC1 DC0
DC2 DC1 DC0
T4
T4
T4
T4
T4
T4
T4
T4
U4
D4
K4
X
4
x
x
x
x
1
x
x
x
x
x
bit set. When a SPI error is detected, the 33789 will
immediately set SO to a high-impedance state.
RXO
LM4
MR1 MR0 TEN
4LE
4SE
VS1
8
1
0
T3
T3
T3
T3
T3
T3
T3
T3
U3
D3
K3
3
x
0
x
x
x
x
x
x
SPI errors could be caused by:
•An incorrect number of SPI SCK cycles (>16, or <16 but
•Too short of an inter-frame time
>0), while CS is active
BUE ERC
3SE
LM3
VS0
3LE
U2
D2
K2
T2
T2
T2
T2
T2
T2
T2
T2
2
x
x
x
x
x
x
x
7
0
0
LM2
LSR
2LE
2SE
HS
HS
T1
T1
T1
T1
T1
T1
T1
T1
U1
D1
K1
1
x
1
1
x
x
x
x
x
x
ERC
1SE
LM1
LSR
LEV
1LE
6
1
0
EN
U0
D0
K0
T0
T0
T0
T0
T0
T0
T0
T0
0
0
0
x
x
x
x
x
x
x
x
15:0
8A
8B
8C
8D
8E
8F
9A
9B
9C
9D
9E
9F
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
8
5
0
0
Analog Integrated Circuit Device Data
OT4
BST CDF
SS3
SOT DCO
VD3
D7
TS
TS
T7
T7
T7
T7
T7
T7
T7
T7
S7
7
0
0
0
0
x
0
0
0
0
0
OT3
SS2
VD2
4
1
0
D6
T6
T6
T6
T6
T6
T6
T6
T6
S6
6
0
0
0
0
0
0
0
T
0
0
0
0
x
REN RX0
OT2
SS1
BOT
VD1
OFF
OFF
D5
SC
T5
T5
T5
T5
T5
T5
T5
T5
S5
23
23
5
0
0
0
0
0
0
0
0
0
Freescale Semiconductor
Read Data
3
0
0
AIC4 AIC3 AIC2 AIC1 AIC0
BOE
OFF
OFF
OT1
SS0
VD0 MD1 MD0
IGN
D4
S4
T4
T4
T4
T4
T4
T4
T4
T4
13
13
4
0
0
0
0
1
0
0
0
0
lLM4 LM3
RXO
ON2
ON2
2
0
0
4LE
4SE
VS1
WU
D3
T3
T3
T3
T3
T3
T3
T3
T3
S3
3
0
0
0
0
0
0
0
0
3
3
BUE ERC
WS1 WS0
ON1
ON1
3SE
VS0
3LE
D2
S2
T2
T2
T2
T2
T2
T2
T2
T2
2
0
0
x
0
0
0
0
3
3
1
1
0
LM2
LSR
2LE
2SE
OE
HS
HS
D1
T1
T1
T1
T1
T1
T1
T1
T1
S1
1
1
1
1
1
0
1
1
1
1
ERC
0
0
0
1SE
LM1
LSR
1LE
WD
D0
SE
S0
T0
T0
T0
T0
T0
T0
T0
T0
R
0
0
0
0
0
0
0
0
0
0
0
0