s1r72803 Epson Electronics America, Inc., s1r72803 Datasheet - Page 109

• Manufacturer Part Number: s1r72803
• Description: Link/transaction Controller
• Manufacturer: Epson Electronics America, Inc.

9.4.4.2 CPU Write Cycle
Regarding the built-in CPU, refer to the S1C33208/204/202 Technical Manual and S1C33 Family ASIC Macro Manual.
In the built-in CPU core, however, a DMA controller or A/D converter are not integrated; this part is different from the
description on the DMA controller and A/D converter given in the Technical Manual and Macro Manual. Both low-
speed oscillation circuit (OSC1) and high-speed oscillation circuit (OSC4) are not available.
(Wait input)
P_WR
P_D[15:0]
P_A[23:0]
P_P30
P_BCLK
Symbol
P_CE
t
t
t
t
t
t
t
WRD1
WDD1
WRD2
t
t
WDH
WRW
WTH
WTS
t
CE1
CE2
AD
X
_X
X
Address delay time
P_CEx delay time (1)
P_CEx delay time (2)
Wait set-up time
Wait hold time
Write signal delay time (1)
Write data delay time (1)
Write data hold time
Write signal delay time (2)
Write signal pulse width
t
AD
Specification
t
t
WTS
CE1
C
1
t
t
t
WRD1
WDD1
WTH
Next is also wait cycle
C
W
t
WTS
(Wait cycle)
EPSON
t
t
WTH
CYC
(1+WC)–10
*
* WC: Wait cycle signal
Min.
t
29
CYC
–
–
–
0
–
–
0
–
t
WRW
=40ns when bus clock is 25MHz in X2 mode.
C
Next is last cycle
W
t
WTS
(Wait cycle)
t
WTH
Max.
10
8
8
8
–
–
8
–
8
–
Cn (Last cycle)
S1R72803F00A
t
WRD2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
WDH
t
AD
105