s1r72803 Epson Electronics America, Inc., s1r72803 Datasheet - Page 79

• Manufacturer Part Number: s1r72803
• Description: Link/transaction Controller
• Manufacturer: Epson Electronics America, Inc.

Rx DMA Control Register
Bit7..4 Reserved
Bit3 Receive FIFO Empty
Bit2 Receive FIFO Clear
Bit1 Reception Monitor
Bit0 Force Busy
Address Register Name
0x54
When the DMA-FIFO for reception is empty, this bit becomes “0”. When it is not empty, it is “1”. This bit is
read-only and writing to this bit is ignored.
Clears the DMA-FIFO for reception. Writing “1” to this bit clears the FIFO. After clearing it, this bit is
automatically restored to “0”.
Indicates the receive status of ISO. “1” indicates that a receive packet is in reception and “0” indicates that no
receive packet is in reception. This bit is read-only and writing to this bit is ignored.
Setting this bit to “1” can forcedly return an Ack_Busy to a receive packet.
Before performing the RxData Clear or RxHdrClear, be sure to set this bit.
If you set this bit during receiving a packet, the packet operates to complete the reception regardless of to what
extent the packet has been received. It means that a RxDmaCmp interrupt occurs if this packet has been correctly
received. The Ack_busy is continuously returned to the subsequent receive packets.
RxDmaCtl
7:
6:
5:
4:
3: RxFIFOEpty
2: RxFIFOClr
1: RxMon
0: ForceBusy
Bit Symbol
R/W
R/W 0: Normal
W
R
R
0:
0:
0:
0:
0: Rx FIFO Empty
0: Normal
0: Rx Stop
EPSON
Description
1:
1:
1:
1:
1: Non Empty
1: Rx FIFO Clear
1: Rx Run
1: Busy
H.Rst S.Rst B.Rst
S1R72803F00A
0x00 0x00
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