dp8421a National Semiconductor Corporation, dp8421a Datasheet - Page 11

• Manufacturer Part Number: dp8421a
• Description: Microcmos Programmable 256k/1m/4m Dynamic Ram Controller/drivers
• Manufacturer: National Semiconductor Corporation

3 0 Programming and Resetting
3 3 PROGRAMMING BIT DEFINITIONS (Continued)
C6 C5 C4
1 0 1
1 1 0
1 1 1
C3
0
1
C2 C1 C0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
R9
0
1
R8
0
1
R7
0
1
R6
0
1
Symbol
RAS and CAS Configuration Modes (Continued)
RAS and CAS pairs are selected by B1 ECASn must be asserted for CASn to be asserted
B1
B1
B0 is not used during an access
No error scrubbing
RAS singles are selected by B0 – 1 CAS0 – 3 are all selected ECASn must be asserted for CASn to be
asserted
B1
B1
B1
B1
No error scrubbing
RAS and CAS singles are selected by B0 1 ECASn must be asserted for CASn to be asserted
B1
B1
B1
B1
No error scrubbing
Refresh Clock Fine Tune Divisor
Divide delay line refresh clock further by 30 (If DELCLK Refresh Clock Clock Divisor
refresh period)
Divide delay line refresh clock further by 26 (If DELCLK Refresh Clock Clock Divisor
refresh period)
Delay Line Refresh Clock Divisor Select
Divide DELCLK by 10 to get as close to 2 MHz as possible
Divide DELCLK by 9 to get as close to 2 MHz as possible
Divide DELCLK by 8 to get as close to 2 MHz as possible
Divide DELCLK by 7 to get as close to 2 MHz as possible
Divide DELCLK by 6 to get as close to 2 MHz as possible
Divide DELCLK by 5 to get as close to 2 MHz as possible
Divide DELCLK by 4 to get as close to 2 MHz as possible
Divide DELCLK by 3 to get as close to 2 MHz as possible
Refresh Mode Select
RAS0 – 3 will all assert and negate at the same time during a refresh
Staggered Refresh RAS outputs during refresh are separated by one positive clock edge Depending on the
configuration mode chosen either one or two RASs will be asserted
Address Pipelining Select
Address pipelining is selected The DRAM controller will switch the DRAM column address back to the row
address after guaranteeing the column address hold time
Non-address pipelining is selected The DRAM controller will hold the column address on the DRAM address
bus until the access RASs are negated
WAIT or DTACK Select
WAIT type output is selected
DTACK (Data Transfer ACKnowledge) type output is selected
Add Wait States to the Current Access if WAITIN is Low
WAIT or DTACK will be delayed by one additional positive edge of CLK
WAIT or DTACK will be delayed by two additional positive edges of CLK
e
e
e
e
e
e
e
e
e
e
0 during an access selects RAS0 – 1 and CAS0 – 1
1 during an access selects RAS2 – 3 and CAS2 – 3
0 B0
0 B0
1 B0
1 B0
0 B0
0 B0
1 B0
1 B0
e
e
e
e
e
e
e
e
0 during an access selects RAS0 and CAS0 – 3
1 during an access selects RAS1 and CAS0 – 3
0 during an access selects RAS2 and CAS0 – 3
1 during an access selects RAS3 and CAS0 – 3
0 during an access selects RAS0 and CAS0
1 during an access selects RAS1 and CAS1
0 during an access selects RAS2 and CAS2
1 during an access selects RAS3 and CAS3
(Continued)
11
Description
e
e
2 MHz
2 MHz
e
e
15 ms
13 ms