dp8421a National Semiconductor Corporation, dp8421a Datasheet - Page 27

• Manufacturer Part Number: dp8421a
• Description: Microcmos Programmable 256k/1m/4m Dynamic Ram Controller/drivers
• Manufacturer: National Semiconductor Corporation

5 0 Refresh Options
5 3 EXTENDING REFRESH
The programmed number of periods of CLK that refresh
RASs are asserted can be extended by one or multiple peri-
ods of CLK Only the all RAS (with or without error scrub-
bing) type of refresh can be extended To extend a refresh
cycle the input extend refresh EXTNDRF must be assert-
ed before the positive edge of CLK that would have negated
all the RAS outputs during the refresh cycle and after the
positive edge of CLK which starts all RAS outputs during the
refresh as shown in Figure 19 This will extend the refresh to
the next positive edge of CLK and EXTNDRF will be sam-
pled again The refresh cycle will continue until EXTNDRF is
sampled low on a positive edge of CLK
FIGURE 19 Extending Refresh with the Extend Refresh (EXTNDRF) Input
FIGURE 20b Clearing the Refresh Counter during Burst
(Continued)
FIGURE 20a Clearing the Refresh Address Counter
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5 4 CLEARING THE REFRESH ADDRESS COUNTER
The refresh address counter can be cleared by asserting
RFSH while DISRFSH is negated as shown in Figure 20a
This can be used prior to a burst refresh of the entire memo-
ry array By asserting RFSH one period of CLK before
DISRFSH is asserted and then keeping both inputs assert-
ed the DP8420A 21A 22A will clear the refresh address
counter and then perform refresh cycles separated by the
programmed value of precharge as shown in Figure 20b An
end-of-count signal can be generated from the Q DRAM
address outputs of the DP8420A 21A 22A and used to ne-
gate RFSH
TL F 8588 – 72
TL F 8588 – 71
TL F 8588 – 73