dp8421a National Semiconductor Corporation, dp8421a Datasheet - Page 31

• Manufacturer Part Number: dp8421a
• Description: Microcmos Programmable 256k/1m/4m Dynamic Ram Controller/drivers
• Manufacturer: National Semiconductor Corporation

7 0 RAS and CAS Configuration Modes
The DP8420A 21A 22A allow the user to configure the
DRAM array to contain one two or four banks of DRAM
Depending on the functions used certain considerations
must be used when determining how to set up the DRAM
array Programming address bits C4 C5 and C6 along with
bank selects B0 – 1 and CAS enables ECAS0 – 3 deter-
mine which RAS or group of RASs and which CAS or group
of CASs will be asserted during an access Different memo-
ry schemes are described The DP8420A 21A 22A is spec-
ified driving a heavy load of 72 DRAMs representing four
banks of DRAM with 16-bit words and 2 parity bits The
DP8420A 21A 22A can drive more than 72 DRAMs but the
AC timing must be increased Since the RAS and CAS out-
puts are configurable all RAS and CAS outputs should be
used for the maximum amount of drive
FIGURE 26b DRAM Array Setup for 32-Bit 1 Bank System (C6 C5 C4
FIGURE 26a DRAM Array Setup for 32-Bit System (C6 C5 C4
or C6 C5 C4
e
0 1 1 No Error Scrubbing during Programming)
31
Figures 26a and 26b In systems with a word size of 16 bits
7 1 BYTE WRITING
By selecting a configuration in which all CAS outputs are
selected during an access the ECAS inputs enable a single
or group of CAS outputs to select a byte (or bytes) in a word
size of up to 32 bits In this case the RAS outputs are used
to select which of up to 4 banks is to be used as shown in
the byte enables can be gated with a high order address bit
to produce four byte enables which gives an equivalent to 8
banks of 16-bit words as shown in Figure 26d If less memo-
ry is required each CAS should be used to drive each nibble
in the 16-bit word as shown in Figure 26c
e
e
1 1 0 during Programming)
0 0 0 Allowing Error Scrubbing
TL F 8588 – D0
TL F 8588 – C9