z86230 ZiLOG Semiconductor, z86230 Datasheet - Page 11

• Manufacturer Part Number: z86230
• Description: Advanced Violence Blocking And Ntsc Line 21 Xds
• Manufacturer: ZiLOG Semiconductor

1.1.1 Input Signals
1.1.2 Video Input Signal Processing
1.1.3 Voltage-Controlled Oscillator (VCO) and One-Shot
1.1.4 Timing and Counting Circuits
1.1.5 Command Processor
PS000400-TVC0499
B
The Composite Video input should be a signal which is nominally 1.0 Volt p-p,
with sync tips negative and band limited to 600 kHz. The Z86230 operates with an
input level variation of ±3 dB.
The
(VCO) close to the required operating frequency.
The Composite Video input is AC-coupled to the device where the sync tip is
internally clamped to a fixed reference voltage.
The Data Slicer extracts a clean CMOS-level data signal by slicing the signal at its
midpoint. The slice level is established on an adaptive basis during Line 21.
The Sync Slicer processes the clamped Composite Video signal to extract Com-
posite Sync. This signal is used to lock the internal logic to the incoming video.
The slice level is stored on the sync slice capacitor,
The Data Clock Recovery circuit operates in conjunction with the
Lock
appears,
reclock the sliced data). When phase lock is established,
a change in the video signal occurs.
All internal timing and synchronizing signals are derived from the on-board 12-
MHz VCO. Its output is the
counter chains.
The One-Shot circuit produces a horizontal timing signal derived from the incom-
ing video.
The VCO exhibits stable gain characteristics and good power supply rejection.
The
signal is further divided in the line counter (
CNTR
the control functions required for proper operation.
The Command Processor controls the manipulation of the data for storage. During
the recovery time, the command processor, in conjunction with the data recovery
circuits, recovers the XDS data.
LOCK
HIN/XIN
DCLK
circuit. These circuits produce a data clock (
D
) to produce the various decodes used to establish vertical lock and to time
IAGRAM AND
DCLK
is divided to generate the horizontal timing signals
input signal is required to bring the voltage-controlled oscillator
phase lock is achieved during the clock run-in burst (used to
Z86230—PRELIMINARY
O
PERATIONAL
DCLK
O
VERVIEW
signal used to drive the Horizontal and Vertical
LINE CNTR
DCLK
CSYNC
A
) and, when Line 21 code
) and field counter (
DCLK
RCHITECTURAL
.
H
is maintained until
and
Horizontal (H)
2H
O
.The
VERVIEW
FLD
H
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