z86230 ZiLOG Semiconductor, z86230 Datasheet - Page 48

• Manufacturer Part Number: z86230
• Description: Advanced Violence Blocking And Ntsc Line 21 Xds
• Manufacturer: ZiLOG Semiconductor

8.5.2 HIN/XIN Signal Input
Table 39. HIN/XIN Signal Input
48
Mode
1. HIN
Input
2. XIN
Input
(Video Lock Mode)
(HIN Lock Mode)
(XTAL)
(Clock)
E
LECTRICAL
T
Parameter
H Timing
Vertical Sync
Signal
Minimum Signal-
to-Noise
Ratio to Composite
Video
ABLE
C
HARACTERISTICS
38. N
Parameter
Amplitude
Polarity
Frequency
Amplitude
Polarity
Frequency
Frequency
Frequency
tolerance
Amplitude
Frequency
ON
-S
Z86230—PRELIMINARY
TANDARD
Conditions
Phase Step (Head Switch) ±10 µs maximum
Fh Deviation (long term) ±0.5% maximum
Fh p-p Deviation (short term) ±0.3% maximum
The internal sync circuits lock to all 525- or 625-line
signals that exhibit a vertical sync pulse that meets the
following conditions:
The Z86230 functions down to a 25 dB signal-to-noise
ratio (CCIR-weighted) with one error per row or better
at that level.
Input
1. It is at least 3H ±0.5H wide.
2. It starts at the proper 2H boundary for its field.
3. If equalizing pulse serrations are present, they
V
IDEO
must be less than 0.125H in width.
Conditions
CMOS level signal where Low
Any
15,734.263 Hz @ 3%
CMOS level signal where Low
Any
Same as Display Horizontal Flyback (HFB)
pulse
32.768 KHz
±20ppm @ T
CMOS level signal where Low
32.768 kHz ±2%
S
IGNALS
A
= 25C, CL = 12.5pF
E
LECTRICAL
PS000400-TVC0499
C
HARACTERISTICS
0.2 V
0.2 V
0.2 V
CC
CC
CC